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How to set FSRF1 bit in PBIST

Pashan None
Genius 5660 points

Hello Support,

If I select PBIST Test to run using Test Pattern MARCH13N_RED_TEST_PATTERN_TWO_PORT for RAM Group 1 [PBIST_ROM], then I get FSRF0 bit SET and FSRF1 Bit CLEAR.

I have taken the EXAMPLE Code as defined in the function pbistSelfCheck() within sys_startup_recommended.c module of spna106a.zip contents for the above mentioned condition.

Can you please tell me which Test Pattern and RAM Group combination will make FSRF1 bit SET at the end of PBIST Selfcheck RUN completion?

Thank you.

Regards

Pashan

 

  • 0
    TI__Guru 59540 points

    Hello Pashan,

    I am currently looking into your question and will get back with you in a short time.

  • 0 in reply to Chuck Davenport
    TI__Guru 59540 points

    Hello Pashan,

    The FSRF0 and FSRF1 bits are related to he PBIST logic. It is capable of using 2 ports (note this is different than the single or dual port RAM designation) to check the RAM. Each of the 2 ports are for 32bits so in the Hercules family of products which has 64-bit wide RAM banks, both ports are used. As such the FSRF1 bit can be set by any of the test patterns on any of the RAM groups if the failure ocurrs in the 32-bits tested by port 1 of the PBIST module.

  • 0 in reply to Chuck Davenport
    Genius 5660 points

    Hello Chuck,

    You didn't answer my original question.

    Question is WHICH Test Pattern and WHICH RAM Group combination will always SET FSRF1 Bit unconditionally even though there is no real failure but wrong Test Pattern is selected.

    I can easily set FSFR0 bit by selecting wrong Test Pattern.

    Please help me with FSRF1 Bit using wrong Test Pattern.

    Thank you.

    Regards

    Pashan

     

  • 0 in reply to Pashan None
    TI__Guru 59540 points

    Hello Pashan,

    I do believe that I did answer the question. Both ports are used in all of the algorithms due to the RAM widths. The generation of FSRF0 or FSRF1 error flags is dependent on where the failure in the RAM under test is located. The only way to guarantee a failure on one or the other port is to physically create a fault in RAM corresponding to the 32-bits tested through the specific port.

  • 0 in reply to Chuck Davenport
    Genius 5660 points

    Hello Chuck,

    I am not looking for Physical Failure condition to trigger FSRF1 Bit.

    I am looking for something like pbistSelfCheck() function of snpa106a.zip contents, where a wrong test pattern is selected and FSRF0 Bit is set without any real physical fault in the system.

    Please help me with a modified pbistSelfCheck() function which will set FSRF1 instead of FSRF0 bit.

    Let me know.

    Thank you.

    Regards

    Pashan

     

  • 0 in reply to Pashan None
    Genius 5660 points

    Hello Support,

    Can you please tell me how to test FSRF1 Bit SET condition?

    Thank you.

    Regards

    Pashan

  • 0 in reply to Pashan None
    TI__Guru 59540 points

    Hello Pashan,

    I wanted to give a quick update on this open topic. Design is currently running through their simulation and RTL analysis to idenify how to force the FSRF1 bit to be set. I will post the answer here as soon as it is available. My apologies for the delay in resolving your question.

  • 0 in reply to Chuck Davenport
    TI__Guru 59540 points

    Hello Pashan,

    My apologies for the long delay, but we have finally recieved the feedback from the design team's analysis of the FSRF1 bit being set during PBIST execution. Below is the message from the team on their analysis.

    "We did multiple experiments to force error on FSRF1 bit but did not successes.

    Upon consulting Rajat (from PBIST flow team) we came to know that the way in which we integrate the memory data path (MDP) and type of algorithms we use will not set fail on FSRF1 bit. So, as per our MDP architecture and type of algorithms we use the fail will always be set ONLY on FSRF0.  "

    This analysis is applicable to all TMS570LS31x/21x, TM570LS12x/11x, and TMS570LS043x/033x families of devices as well as all RM48x, RM46x, and RM42x families of devices.

    Again, my apologies for the delay in getting a response back to you. Hopefully this will close the issue for you.