HALCOgen generated function _coreInitRegisters_ in sys_core.asm file:
This function implementation in the the application report SPNA119 and the project created using the HALCogen tool are differs.
Application report: http://www.ti.com/lit/an/spna119/spna119.pdf
Below is the asm code from application report for initialising the core resgisters in system mode.
mov r0, #0x2DF
Configure core to system mode for initialization
msr cpsr, r0
mov r1, #0
mov r2, #0
mov r3, #0
mov r4, #0
mov r5, #0
mov r6, #0
mov r7, #0
mov r8, #0
mov r9, #0
mov r10, #0
mov r11 #0
mov r12 #0
mov r13 #0
As per the above code 0x2DF is copied to CPSR. i.e., bit 8 "Imprecise abort enable bit" of CPSR is 0.
But in the HALCOgen code for "_coreInitRegisters_", this bit is always 1.
mov r0, lr
mov r1, #0x03D0
mov r2, #0x0000
mov r3, #0x0000
mov r4, #0x0000
mov r5, #0x0000
mov r6, #0x0000
mov r7, #0x0000
mov r8, #0x0000
mov r9, #0x0000
mov r10, #0x0000
mov r11, #0x0000
mov r12, #0x0000
orr r13, r1, #0x0001 ; (cpsr is loaded with 3D1 for configuring core to FIQ mode, in any case bit 8 is 1 always in all modes.. why?)
msr cpsr_cxsf, r13
msr spsr_cxsf, r13
In the HALCOgen code, the core is not configured to system mode as done in application report. why?
