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TMS570LS3137ZWT freeRTOS MPU

Martin Zeman
Intellectual 820 points
Other Parts Discussed in Thread: HALCOGEN

Hi,

I could use your help understanding the freeRTOS MPU settings that Halcogen generated for my TMS570LS3137ZWT. The code in question is this:

	/* First setup the entire flash for unprivileged read only access. */
	prvMpuSetRegion(portUNPRIVILEGED_FLASH_REGION,  0x00000000, portMPU_SIZE_4MB | portMPU_REGION_ENABLE, portMPU_PRIV_RO_USER_RO_EXEC | portMPU_NORMAL_OIWTNOWA_SHARED);

	/* Setup the first 32K for privileged only access.  This is where the kernel code is
	placed. */
	prvMpuSetRegion(portPRIVILEGED_FLASH_REGION,  0x00000000, portMPU_SIZE_32KB | portMPU_REGION_ENABLE, portMPU_PRIV_RO_USER_NA_EXEC | portMPU_NORMAL_OIWTNOWA_SHARED);

	/* Setup the privileged data RAM region.  This is where the kernel data
	is placed. */
	prvMpuSetRegion(portPRIVILEGED_RAM_REGION,  0x08000000, portMPU_SIZE_512KB | portMPU_REGION_ENABLE, portMPU_PRIV_RW_USER_RO_EXEC | portMPU_NORMAL_OIWTNOWA_SHARED);

	/* Default peripherals setup */
	prvMpuSetRegion(portGENERAL_PERIPHERALS_REGION,  0xF0000000,
					portMPU_SIZE_256MB | portMPU_REGION_ENABLE | portMPU_SUBREGION_1_DISABLE | portMPU_SUBREGION_2_DISABLE | portMPU_SUBREGION_3_DISABLE | portMPU_SUBREGION_4_DISABLE,
					portMPU_PRIV_RW_USER_RW_NOEXEC | portMPU_DEVICE_NONSHAREABLE);

	/* Privilege System Region setup */
	prvMpuSetRegion(portPRIVILEGED_SYSTEM_REGION,  0xFFF80000, portMPU_SIZE_512KB | portMPU_REGION_ENABLE, portMPU_PRIV_RW_USER_RO_NOEXEC | portMPU_DEVICE_NONSHAREABLE);

The flash, peripheral and system region settings I do understand but not the RAM. The TMS570LS3137ZWT only has 256 KB of integrated RAM but halcogen sets the size to 512KB. Why is that?

Also, this sentence from the RTOS website confuses me:

  • The data maintained by the RTOS kernel (all non stack data that is private to the FreeRTOS source files) is located in a region of RAM that can only be accessed while the microcontroller is in Privileged mode.

If the whole RAM is taken up by the privileged kernel section then where is the stack going to be placed?
I'd appreciate if someone could clear it up for me.
Thanks

  • 0
    TI__Mastermind 22715 points

    Hi, there.

    I have forwarded your question to Halcogen team. They will provide the answer to you shortly.

    Thanks and regards,

    Zhaohong

  • 0
    TI__Genius 14205 points

    Hi Martin,

    Following are my comments

    1) You are right it should be 256KB not 512KB. But this should not affect your code function.This file is a static which adhears to superset device which has 512. In next release we will make it Dynamic based on device choosen.

    2) The whole RAM is configured with MPU region 2 which has less priority to the MPU region configured during Createtask. Createtask configures region 4 with Whole RAM non-privledged and REgion 5 to Protect RTOS Kernel data ( KRAM). So it is taken care.

    The implemention is made this way to accomodate both Restricted and Non-Restricted Tasks implementation.

    Sorry the comments "/* Setup the privileged data RAM region.  This is where the kernel data
    is placed. */" mislead you, we will fix that too.

  • 0 in reply to Prathap
    Intellectual 820 points

    Hi Prathap,

     

    thanks for clearing that up. Talking abour priorities I'd like to ask about the configKERNEL_INTERRUPT_PRIORITY and the configMAX_SYSCALL_INTERRUPT_PRIORITY macros which are not defined in the port.

    The TMS570LS317ZWT only has two levels of interrupt priorty. So I'd like to ask what their relation to the OS port is? At which priority does the tick timer run? And to which level is the configMAX_SYSCALL_INTERRUPT_PRIORITY set?

    Thanks

  • 0 in reply to Martin Zeman
    TI__Genius 14205 points

    Hi Martin,

    Yes you are right configMAX_SYSCALL_INTERRUPT_PRIORITY and configKERNEL_INTERRUPT_PRIORITY are not needed for CortexR4, They are used for Cortex Mx cores. All interrupts ( IRQ mapped channels) are at same priority at CortexR4 level,  I would recommend to map the interrupt channels to FIQ incase you want some interrutps to be enabled even while entering critical section of the code.