Feedback on EK-TM4C129 Expanded Memory Option Booster Pack

Amit,

Thanks for making these available. We’re working on an LCD controller design and being able to directly use SDRAM is of an enormous value to us. Originally, I was debating between using just enough SRAM (for the frame buffer) and NOR Flash (for assets) in Host Bus 16 mode, or to use a large amount of SDRAM and QSPI flash, then just cache assets from the QSPI flash to the SDRAM on startup. I’ve got one of your boards coming from OSHPark, so it’ll be a good test to see if the latter method will work for us (which I suspect it will).

I’ve got a question about the code provided with the TM4C129SDRAMNVM package. In ektm4c129_qssi_example.c you’re using SSI1, but according to the TM4C129x errata, that port can *only* be used in legacy mode! I thought, surely you hadn’t actually connected the QSPI flash to that port on the actual board, but sure enough, you have… So, am I missing something here or did you goof? Because if it can’t actually be used in quad-SPI mode, it’s not a very good evaluation, is it? =/

Thanks,
Timothy

Hello Timothy

Timothy Brown said:

We’re working on an LCD controller design and being able to directly use SDRAM is of an enormous value to us.

I would like to point the errata LCD#02 and EPI#01. They may seem a bottleneck but only when a high performance raster LCD panel requiring a very high refresh rate is to be used along with code execution. With smart panel or LIDD mode this can be easily managed.

Timothy Brown said:

then just cache assets from the QSPI flash to the SDRAM on startup

Could you please clarify the same?

Timothy Brown said:

In ektm4c129_qssi_example.c you’re using SSI1, but according to the TM4C129x errata, that port can *only* be used in legacy mode

Yes, we are revisiting the errata to see why this was issues and root cause for the same. So probably you may see an updated in the errata revision. However the design does work, but if you are still concerned about the errata, you may want to switch to another SSI port on the final design.

Regards

Amit

Amit Ashara said:

I would like to point the errata LCD#02 and EPI#01. They may seem a bottleneck but only when a high performance raster LCD panel requiring a very high refresh rate is to be used along with code execution. With smart panel or LIDD mode this can be easily managed.

Yes, I’ve seen these. Unfortunately, this will be driving a high performance raster panel, at a high frame rate. The entire goal of the project is to create smart panel that the end user can easily preload with assets (graphics, fonts, etc.) and drive over a low bandwidth serial link (I2C, SPI, UART, CAN). Code execution should be able to work out of the main flash memory. The SDRAM would be used for cacheing assets (fonts, graphics, etc.) and the frame buffer. Hopefully we can work around those two issues.

Hello Timothy,

Thanks for the clarifications and it does help working around the errata's for sure.

For the last one it may be removed after we correctly ascertain the cause for which it was put in the document.

Regards
Amit

Hi Amit,

I am looking to add more SRAM to my development board. Can you please let me know whether you have item #1 DM-TM4C129:X SDRAM Only option is available to order. Please let me know the procedure/link to order also.

Thanks.

Regards,
Piraba

Hello Piraba

The memroy boards are not orderable. The Manufacturing files have been released on the respective TI Design which can be used to manufacture and assemble the boards

Hi Amit,

Thanks for the response. Can you please provide the link to download this design if possible?

Regards,
Piraba

Never mind. I got it. Thanks.

Regards,
Piraba