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program execution fails when running from external SDRAM on TMDS570LS31HDK

Christophe Breuil
Prodigy 100 points
Other Parts Discussed in Thread: TMDS570LS31HDK, HALCOGEN

Context : CCS Version 6.0.1.00040 under windows 7/64 - TMDS570LS31HDK

Hello,


I'm trying to execute some code from external SDRAM on TMDS570LS31HDK and execution crashes immediately, though I'm able to read/write to SDRAM.

During the debug session we can see that the micro jumps to SDRAM entry point, but the next assembly step leads to a crash.

In the attached archive, you wil find the CCS project and a dump a registers state before/after the crash.

I don't know in wich direction to investigate, and your help will be appreciated !


regards,


christophe2806.emif_c2.zip

  • 0
    TI__Guru 72500 points

    Did you program the MPU to allow instruction execution from the SDRAM address space? By default the addresses above 0x80000000 do not allow code execution. See section 7.1 of the ARM Cortex R4F TRM.

  • 0
    TI__Expert 6985 points

    Christophe,

    Your dump of the registers shows "strange" values for the LR and the Instr. Fault Status Register:

    LR 0x7EC74990 --> strange address

    Cp15_CP15_INSTRUCTION_FAULT_ADDRESS 0x7EC7498C --> Strange Address

    EMIF Chip Select 4 (asynchronous) EMIF select 4 0x68000000 0x6BFFFFFF 64MB 16MB

    There is no memory, that's why you get a (Prefetch) Abort.

    Looking at your main.c it seems that you tried to move one function into the RAM with the following line of code: #pragma CODE_SECTION(finobacci, ".sdram")

    This is fine, but I think you are missing a routine to copy this function or to be exact the section ".sdram" from the FLASH into the external RAM at startup. I guess that's why you see this abort. At least I didn't found such a function from looking at you code.

    Please consider reading this article about this topic:

    For your use case it should be fine, if you modify your Linker Command File as following:

    /* USER CODE BEGIN (4) */

    .sdram   : RUN = SDRAM, LOAD = FLASH0|FLASH1, table(BINIT)

      RUN_START(sdramStartAddr), RUN_END(sdramEndAddr)

    /* USER CODE END */

    Please note, that this automatic copying will take place in line 1023 in sys_startup.c, which is before you initialize the external RAM in line 1067. In other words this will also fail, as the external RAM wasn't initialize at that point in time!

    You should also consider to update your compiler version, the version you are using (5.1.6) is quite old. You can find an overview of the compiler versions here: 

    I would suggest you to update to compiler version 15.12.1.LTS. There we introduced the "ramfunc" attribute feature: processors.wiki.ti.com/.../Placing_functions_in_RAM

    This should help to place functions in the external RAM.

    Best Regards,
    Christian

  • 0 in reply to Christian Herget
    Prodigy 100 points

    Hello Christian,

    Thank you for your answer : it helped us to progress a little bit. The present state of the project is that the processor manages to jump in SDRAM, but we see a weird behaviour : the PC registers is incrementing (in SDRAM address space) but nothing else happens : it seems that the processor is 'reading' the code but not executing it.

    Here is a zip file with the CCS project and a dump of registers that has been done at 4 different times during 'execution' in SDRAM

    6305.emif_c2.zip

    thanks for your support,

    christophe

  • 0 in reply to Christophe Breuil
    TI__Expert 6985 points

    Hi Christophe,

    I looked at the CCS Project you sent and I found some issues with regards to the EMIF.
    I did the fixes in the source code directly, as I didn't had the old HALCoGen version (3.02.02) installed.
    Here is a list of what I did, hope that I didn't missed any change, anyways please do a file based comparison to find all changes I did.

    3482.emif_c2_TI_2016-04-16.zip

    EMIF and System Steup

    EMIF_CLK is limited to 50MHz

    EMIF_CLK is derived from VCLK3, which is 80MHz in your case, no further dividers are available. Thus VCLK3 has to be divided down to 40MHz (1/20ns).

    system.c

    /** - Setup synchronous peripheral clock dividers for VCLK1, VCLK2, VCLK3 */

        systemREG1->VCLKR   = 1U;

        systemREG1->VCLK2R  = 1U;

        systemREG2->VCLK3R  = 3U; /* 160MHz / (3+1) = 40MHz */

    EMIF Setup

    Please compare the files and cross check with ISSI device datasheet.

    MPU Setup

    The MPU Region is and has to be set to Normal type memory, so this is fine. But, the older silicon versions might have an issue with the MPU set to Normal for the EMIF (DEVICE#B064 & DEVICE#B071), but these are fixed in Revision D. However, my HDK has Rev C and works just fine.

    PIN MUX

    pinMuxReg->PINMUX5 = PINMUX_BALL_K18_HET1_0 | PINMUX_BALL_W5_HET1_02 | PINMUX_BALL_V6_HET1_05 | PINMUX_BALL_N5_ETMDATA_26;

    pinMuxReg->PINMUX5 = PINMUX_BALL_K18_HET1_0 | PINMUX_BALL_W5_HET1_02 | PINMUX_BALL_V6_HET1_05 | PINMUX_BALL_N5_EMIF_DATA_10;

     

    pinMuxReg->PINMUX7 = PINMUX_BALL_R6_ETMDATA_29 | PINMUX_BALL_V5_MIBSPI3NCS_1 | PINMUX_BALL_W3_HET1_06 | PINMUX_BALL_R7_EMIF_DATA_14;

    pinMuxReg->PINMUX7 = PINMUX_BALL_R6_EMIF_DATA_13 | PINMUX_BALL_V5_MIBSPI3NCS_1 | PINMUX_BALL_W3_HET1_06 | PINMUX_BALL_R7_EMIF_DATA_14;

     

    pinMuxReg->PINMUX11 = PINMUX_BALL_K17_EMIF_nCS_3 | PINMUX_BALL_M17_EMIF_nCS_4 | PINMUX_BALL_L15_ETMDATA_17 | PINMUX_BALL_P1_HET1_24;

    pinMuxReg->PINMUX11 = PINMUX_BALL_K17_EMIF_nCS_3 | PINMUX_BALL_M17_EMIF_nCS_4 | PINMUX_BALL_L15_EMIF_DATA_1 | PINMUX_BALL_P1_HET1_24;

     

    pinMuxReg->PINMUX19 = PINMUX_BALL_E8_ETMDATA_09 | PINMUX_BALL_B11_HET1_30 | PINMUX_BALL_E10_EMIF_nDQM_0 | PINMUX_BALL_E7_EMIF_ADDR_3;

    pinMuxReg->PINMUX19 = PINMUX_BALL_E8_EMIF_ADDR_4 | PINMUX_BALL_B11_HET1_30 | PINMUX_BALL_E10_EMIF_nDQM_0 | PINMUX_BALL_E7_EMIF_ADDR_3;

    Now the disassembly looks good and the function executes properly:

    finobacci():
    80000000: E92D400E push {r1, r2, r3, lr}
    80000004: E58D1004 str r1, [sp, #4]
    80000008: E58D0000 str r0, [sp]
    75 fin1(x,y);
    8000000c: E59D0000 ldr r0, [sp]
    80000010: E59D1004 ldr r1, [sp, #4]
    80000014: EB000003 bl fin1
    76 fin2(x,y);
    80000018: E59D0000 ldr r0, [sp]
    8000001c: E59D1004 ldr r1, [sp, #4]
    80000020: EB00000C bl fin2
    77 }
    80000024: E8BD800E pop {r1, r2, r3, pc}

    Best Regards,
    Christian

  • 0 in reply to Christian Herget
    Prodigy 100 points

    Hello Christian,

    Thanks a lot for your answer : we took into account your remarks and it solved our issue !!

    The code is now executing as expected in SDRAM !

    Best regards

    christophe

  • 0 in reply to Christophe Breuil
    TI__Expert 6985 points
    Christophe,

    You are welcome, could you please mark my last post with the Verify Answer button so it gets closed.

    Thanks,
    Christian