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RM57L843: Self Test Documentation

Dmitri Zakharevski59
Intellectual 905 points
Part Number: RM57L843
Other Parts Discussed in Thread: HALCOGEN

Hello,

I have written some self tests based off the texas instruments safety package for the RM57 but am looking for documentation around some of the hidden registers used and the tests them selves

Specifically what do the following lines do in the PBIST Self check:

/* These registers are all undocumented */
*(volatile uint32_t *)0xFFFFE400U = 0x4C000001U;
*(volatile uint32_t *)0xFFFFE440U = 0x00000075U;
*(volatile uint32_t *)0xFFFFE404U = 0x4C000002U;
*(volatile uint32_t *)0xFFFFE444U = 0x00000075U;
*(volatile uint32_t *)0xFFFFE408U = 0x4C000003U;
*(volatile uint32_t *)0xFFFFE448U = 0x00000075U;
*(volatile uint32_t *)0xFFFFE40CU = 0x4C000004U;
*(volatile uint32_t *)0xFFFFE44CU = 0x00000075U;
*(volatile uint32_t *)0xFFFFE410U = 0x4C000005U;
*(volatile uint32_t *)0xFFFFE450U = 0x00000075U;
*(volatile uint32_t *)0xFFFFE414U = 0x4C000006U;
*(volatile uint32_t *)0xFFFFE454U = 0x00000075U;
*(volatile uint32_t *)0xFFFFE418U = 0x00000000U;
*(volatile uint32_t *)0xFFFFE458U = 0x00000001U;

/*Run PBIST*/

*(volatile uint32_t *) FFFFE56CU = 1;

All of the registers used are undocumented. Is there supplemental documentation for these health tests?

Thanks

Dmitri

  • 0
    TI__Guru 59540 points

    Hello Dmitri,

    Can you provide more details on where this code is found? I haven't been able to locate it in the files for the SafeTI Diag Lib v2.3.1.

  • 0
    Intellectual 905 points
    Part of the pbistSelfCheck method not implemented in TMS570 and RM57 Safety manual currently, but called out in the Safety Manual 7.134 Software Test of PBIST. www.ti.com/.../spnu540a.pdf
  • 0 in reply to Dmitri Zakharevski59
    TI__Guru 59540 points

    Hello Dmitri,

    Thanks for the additional information. I see now that this is from the safe init routines provided with some of the devices in Halcogen. Note that this is not provided in the RM57 and TMS570LC43xx options since these devices are very different. It is strongly recommended to utilize the SafeTI Diagnostic Library available at this link: .

    I've also asked our SW lead for halcogen to have a look at this as well to see if they can provide further information as to the purpose of these registers and the addresses used. From my perspective this code would represent an issue in any production code and even more so in any Functional Safety related code since the TI TRM states the offsets 000h-15Ch frame are reserved and specifically note not to write to these registers.

  • 0 in reply to Chuck Davenport
    Intellectual 905 points

    Hi Chuck,

    The code is from the RM48 Safe TI Library and the registers are also listed as reserved in the device data sheet:

     Section 7.5.

    The code does execute and with some modification and is seemingly executing a PBIST self check.

  • 0 in reply to Dmitri Zakharevski59
    TI__Genius 14205 points

    Hi Dmitri,

    That is correct, These are internal register writes that TI does not want to expose to customers. But purpose of these register writes are to configure and execute PBIST in a custom way to hit the errata PBIST#4 workaround precisely and quickly.

    Please refer the latest device Errata file spnz214c.pdf for description on Errata PBIST#4. 

  • 0 in reply to Dmitri Zakharevski59
    TI__Guru 59540 points
    Dmitri,

    To followup on Prathaps comments. The silicon revision the linked errata document applies to is silicon revision A. The advisory PBIST#4 indicated in this errata document has been repaired on silicon registion B. Therefore, the errata work around that Prathap has indicated is not needed on silicon revision B.

    However, to address the use of these registers in the PBIST self test routing you have noted, these registers are used to define a custom algorithm. In this case, the custom algorithm that is created for the PBIST self test is designed to generate a failure on PBIST. This failure then is proof that the PBIST module is able to signal the system when a failure occurs. Although this is slightly different implementation than what is described in the safety manual, it still complies with the spirit of the test for diagnostic. From a customer point of view, this sequence of register writes can be treated as a black box with the output being a PBIST Fail.

    Note that this is no different than the treatment of any other ROM based algorithm that is used by PBIST except that are able to see these register writes in the diagnostic library code. Under normal use of PBIST you would configure PBIST to use a specific algorithm for testing. Once configured, the ROM based test would configure the same registers to perform the specified algo, but this activity happens "behind the scenes" as part of the PBIST implementation and the PBIST ROM.
  • 0 in reply to Chuck Davenport
    Intellectual 905 points

    Thank you Chuck, Prathaps.

    Is a built in algorithm going to be available in the future?

    Thanks,

    Dmitri

  • 0 in reply to Dmitri Zakharevski59
    TI__Guru 59540 points
    Dmitri,

    There are no plans to change the way this is currently implemented in the Hercules family. This would be a new silicon and new ROM space definition that would require a complete overhaul of the silicon design. Perhaps in a follow-on device.
  • 0 in reply to Chuck Davenport
    Intellectual 905 points

    Thank you, this answers all of my questions.