We need to sample both QEI position counters at "exactly" consistent intervals of 1 ms, where "exactly" means reducing timing variance as much as practical. For example if samples are usually taken around 1 ms apart but sometimes 1.5 ms and sometimes 0.5 ms, that will throw off our sampling and give unacceptable performance.
In the past, we used a quadrature counter IC that featured a separate holding register. When sent a timing pulse, the IC would copy the instantaneous counter register to this holding register, i.e., "latch" the value. This same timing pulse would trigger an interrupt in our MCU, which would read the saved value from the IC's holding register. In this manner, timing variances of software execution had no effect on QEI sampling: the important thing is that the value was "latched" on time. For the pedantic: yes, there were certainly timing variances in the hardware, but these were on the order of a few nanoseconds, many orders of magnitude smaller than variances introduced by software.
TM4C does not appear to offer such a holding register "in hardware," hence this question. The "best" solution we've thought of is the obvious one: Use a Timer peripheral to trigger an interrupt at regular intervals, set this interrupt to highest priority, and sample the QEI in this interrupt. Of course there are still various "gotchas" in software that could throw off the timing, such as other interrupts fixed to negative priorities.
Is that truly the "best" solution on TM4C? Is there some way to use timer-triggered DMA to copy *BOTH* QEI position counters to variables in memory with less timing variance? Or perhaps some other possibility we've overlooked?
