Other Parts Discussed in Thread: LM4041-N, INA240, TM4C1294KCPDT, TM4C1294NCPDT
Conditions of issue:
1. GPTM 12 bit in 1/2 wide input edge down count of incoming tachometer signal. Every 210 edge counts @4PPS drives an interrupt and triggers One Shot timer set for 201Hz used for match count variable updates via the interrupt handler reloading the same 201Hz time each cycle. That cycle drifts greatly when ever PMW0 becomes active.
2. The Oneshot handler uses GPTM edge counter register to determine the current count of edge input events by subtracting GPTMTnR from the value of GPTMTnILR register and updates the match count static variable used in the edge count frequency of interrupts. The hander then reloads the Oneshot @201Hz for the next cycle. This proves a faster method to update RPM digital display than waiting 60 seconds each interval and counting the same number of preset edges to produce edge count interrupts relative to CCP1 input frequency.
3. The Oneshot speed updates are stable and accurate long as the PWM0 peripheral is not using NVIC or GPIO ports. When PWM0 duty cycle accelerates so does the frequency of the Oneshot reload, 201Hz accelerate but CCP1 input remains steady 102Hz or 1671 RPM. How can that occur if the same CCP1 (102Hz edge counts) is maintained and there is virtually no phase jitter in either rising or falling edges >1us when PWM0 is outputting on GPIO pins? Also tested POS edge only event counts which have 0% phase jitter at 102Hz, same false triggering CCP1 occurs.
4. Verified 201hz pulse is produced via GPIO pin placed inside edge count interrupt handler, accelerate and become steady 1us pulses. Very difficult to measure a 201Hz strobe pulse other than by human eye/brain witnessing the frequency of a single strobe pulse incorrectly accelerates as the CCP1 edge count remains static.
5. GPTM edge count and Oneshot timers have been synchronized after both were configured and each have same INT priority level 0x40, INT51 / INT36 respectively.
Q: Possible GPIO pin MUX value for one of the PWM peripheral GEN pins is internally MUX crossed with CCP1 of GPTM edge counts input?
Q: How else can PWM0 interrupt/ADC0 triggers or GPIO pins so seriously impact CCP1 input of GPTM-0 or Oneshot GPTM-3?
A: 5.10.2018; EXTERNALLY
// Taco input PL5:TM0CCP1 MAP_GPIOPinConfigure(GPIO_PL5_T0CCP1); MAP_GPIOPinTypeTimer(GPIO_PORTL_AHB_BASE, GPIO_PIN_5);
//Enable PD1 pin 2 for COMP1 Co1 (Digital) GPIO Output MAP_GPIOPinConfigure(GPIO_PD1_C1O); GPIOPinTypeComparatorOutput(GPIO_PORTD_AHB_BASE, GPIO_PIN_1);
