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Unable to find NHET RAM Access Wait State for CPU Read/Write Access Information within TRM

Pashan
Intellectual 715 points

Hello,

In the "spnu189h.pdf " document for SYS Moduie related to TMS470R1 devices, there is a register called SMCR1 for HET RAM CPU Access Wait State.

I could not find similar information for NHET RAM CPU Access Wait State definition within spnu489a.pdf document.

Please help.

Thank you.

Regards

Pashan

 

  • 0
    TI__Genius 13810 points

    Pashan,

    NHET access its RAM does not need waitstates.

    Once the CPU access NHET RAM is conflict with NHET's access, the wait states for CPU access will be automatically added.

    Try to make it simple, you don't need to do anything about the waitstates for NHET device. Everything is handled internally.

    Regards,

    Haixiao

  • 0 in reply to Haixiao Weng
    Intellectual 715 points

    Hello Haixiao,

    In the "spnu199d.pdf" document for older HET, on Page 10 [at the end], there is an "Example" section provided.

    That above document mentions that with usual 7 Wait State in SMCR1 for 24 Time-Slot HET Loop Resolution Clock, at a maximum only 3 CPU Accesses are possible per HET Loop Resolution. That leaves 21 Time Slot for HET RAM Program Execution.

    Similar type of analysis I need to perform for NHET in order to determine how many CPU accesses are possible in the WORST Case scenario per NHET Loop Resolution.

    Can you please let me know where in the TRM I can find that information about Worst Case  Wait State in case of collision with NHET RAM Access?

    That will help us to find out how many Time-Slots are available to NHET in case of Continuous CPU Access to NHET RAM.

    Thank you.

    Regards

    Pashan.

     

     

  • 0 in reply to Pashan
    TI__Genius 13810 points

    Pashan,

    NHET has 4 banks. CPU can write to the other banks that the NHET is not accessing. By doing this, the CPU access is taken out of the time-slot calculation.

    Even if in an almost impossible case, all the NHET instructions and CPU are accessing the same bank. The CPU only takes 1 cycle NHET time to write the NHET RAM. And the CPU access to NHET RAM can occur continously (do not need the 7 wait states as in R1x HET).

    Regards,

    Haixiao