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RM46L852: DMA Timing

lars mathisson
Prodigy 40 points
Part Number: RM46L852

I'm trying to figure out how long time a DMA transfer of n bytes take on the RM46.

I assume that it takes some clocks to read the DMA source/dest addres, transfer the data, and update the registers afterwards.

1. Do you have any timing related info regarding this ?

2. If the CPU core and the DMA tries to access the internal memory, who wins this arbitration?

Lars

  • 0
    TI__Guru**** 196176 points

    Hello Lars,

    The DMA runs at system clock (HCLK), and supports up to 64-bit transaction. The internal RAM supports single-cycle read and write accesses in byte/halfword/word, and double-word modes throughout the supported frequency range.

  • 0 in reply to QJ Wang
    Prodigy 40 points

    Ok, but that does not really answer the question.
    How many clocks from a DMA request flag is raised until the transfer starts? 
    How many clocks fram a DMA transfer is done, until a new DMA transfer can be serviced?

    And who wins the arbitration in memory? DMA or Processor ?

    Lars

  • 0 in reply to lars mathisson
    TI__Guru**** 196176 points

    Hello Lars,

    I don't have DMA timing. My estimation is 2~3 HCLK cycles between DMA getting the request and DMA performing the transfer if there is no other DMA pending.

    DMA reads/writes data from/to the TCM RAM through the AXI slave interface. The TCM port can receive requests from the LSU (CPU Load/Store unit), PFU (CPU prefetch unit), and AXI slave (DMA, etc). In most cases, the LSU has the highest priority, followed by the PFU, with the AXI slave having lowest priority. When a higher-priority device is accessing a TCM port, an access from a lower-priority device must stall.