TMS570LC4357: SL_SELFTEST_FLASH（）always failed

Hello,

The MPU setting for Flash should not affect Flash test. For doing flash selftest, the test code should be copied to SRAM and execute from SRAM. Before doing the selftest, please make sure the nERROR led is not ON. If it is ON, please clear the ESM status register. When nERROR is  active, the selft test function returns return FAIL without doing any self test.

Thanks QJ,

I have cpoied code to SRAM and execute from SRAM with #pagma CODE_SWCTION (SL_Selftest_Flash, ".sl_stflash_SRAM"). It always failed just like above.

I also find if I execute SL_Selftest_FLASH(FLASH_ECC_TEST_MODE_1BIT, TRUE, &failInfoFlash) and then execute SL_Selftest_FLASH(FLASH_ECC_TEST_MODE_2BIT, TRUE, &failInfoFlash)，the SL_Selftest_FLASH(FLASH_ECC_TEST_MODE_2BIT, TRUE, &failInfoFlash）failed at line 1337：

1331    if(BIT(ESM_G2ERR_CR5_BUSERR)==(sl_esmREG->SSR2 & BIT(ESM_G2ERR_CR5_BUSERR)))

1332    /*clear nerror */       

1333    _SL_HoldNClear_nError();

1334    sl_esmREG->SSR2 = BIT(ESM_G2ERR_CR5_BUSERR)；   

1335    *flash_stResult = ST_PASS;

1336    } else {

1337    *flash_stResult = ST_FAIL;

1338   }

if I execute SL_Selftest_FLASH(FLASH_ECC_TEST_MODE_2BIT, TRUE, &failInfoFlash) and then execute SL_Selftest_FLASH(FLASH_ECC_TEST_MODE_1BIT, TRUE, &failInfoFlash)，the SL_Selftest_FLASH(FLASH_ECC_TEST_MODE_1BIT, TRUE, &failInfoFlash）failed at line 1121：

1096    if((((((sl_epc->EPCERRSTAT & EPC_ERR_CAM_FULL) == EPC_ERR_CAM_FULL）||

1097              (sl_epc->EPCERRSTAT & EPC_ERR_CAM_OVRFLW) == EPC_ERR_CAM_OVRFLW）||

....……   

1120    } else {             

1121       *flash_stResult = ST_FAIL;     

1122    }

It seems that the first flash selftest always afffects the second flash selftest.

If I setting flash with NORMAL_OINC_NONSHARED, the flash selftest passed.

so any other idea for me ？

Thanks

Hi,

There is a SW bug in SDL. I am not sure it is related to your issues. Please try first.

Hello,

After calling each selftest function, please check if the ESM registers (esmREG->SR[0], esmREG->SR[1], esmREG->SR[2]) have been cleared or not. Flash selftest (ECC 1 bit or ECC 2 bits) injects ECC error (1 bit or 2 bits) which set the flag of single-bit or double-it error in FEDACSTATUS register and ESM status register, and selftest function should clear those flags and disable the diagnostic mode at the end.

1. for ECC 1 bit test. The reading flashBadECC1 generates error:

flashread = *(volatile uint32 *)flashBadECC1; 

2. for ECC 2 bit test. The reading flashBadECC2 generates error:

flashread = *(volatile uint32 *)flashBadECC2;

flashBadECC1 is at 0x00000008, but flashBadECC2 is at 0x00000016. flashread should be updated using the new value in the flash rather than the value in the cache because flashread is from different addresses.

The MPU setting for memory region used for system registers should be device nonsharable or strongly-ordered.

Is this your MPU setting for flash?

Thanks QJ,

I have confirmed ESM register have been cleared before selftest，I can't find FEDACSTATUS register, it means FEDAC_PASTATUS, FEDAC_PBSTATUS and FEDAC_GBLSTATUS， I also confirmed these three register are 0 before selftest.

My mpu settings just like as you posted.

I also tried update SW bug in SDL you provide，it also doesn't work.More, the change point in link you provided or release note spna215a is wrong，because CCS report （*volatile uint32 *）（flashBadECC1 & EPC_CAM_CONTENT_ADDR）as wrong expression.

I guess maybe flash used the value in cache rather than in the flash，so any idea to confirm this？

And  I want to know If I used NORMAL_OINC_NONSHARED and flash SECDED selftest passed ,whether it means SECDED woks fine if I change to NORMAL_OIWTNOWA_NONSHARED or other settings?

If  yes, whether I could choose NORMAL_OINC_NONSHARED finish flash selftest,then I change flash settings to NORMAL_OIWTNOWA_NONSHARED which have a shorter time to finish my application?