TMS570LS3137: Single bit Flash errors

sreenivasan m

Part Number: TMS570LS3137

Hi Team,

We have a couple of questions, please answer them:

1. During startup we enable core Flash ECC using _coreEnableFlashEcc_ method. Are there any restrictions in executing this function call like whether interrupts can be enabled or disabled?
2. We have the following scenario:
Boot S/w which configures HCLK/GCLK as 20 MHz and VCLKx are also 20 MHz. For flash configuration,

/* - Setup flash read mode, address wait states and data wait states */
*flash_frdcntl = (Uint32)(0x00000000UL
| (0UL << 8UL)
| (0UL << 4UL)
| 1UL);

/* - Setup flash bank power modes */
*flash_fbfallback = (Uint32)(0x00000000UL
| ((Uint32)SYS_SLEEP << 14UL) /* BANK 7 */
| ((Uint32)SYS_ACTIVE << 2UL) /* BANK 1 */
| ((Uint32)SYS_ACTIVE << 0UL)); /* BANK 0 */

Now, this Boot loads Loader into RAM and gives control to it. This loader in its startup, configures System clock HCLK/GCLK as 180 MHz ad Vclkx as 20 MHz.
Accordingly Flash configuration will be

/** - Setup flash read mode, address wait states and data wait states */
flashWREG->FRDCNTL = 0x00000000U
| (uint32)((uint32)3U << 8U)
| (uint32)((uint32)1U << 4U)
| 1U;

/** - Setup flash access wait states for bank 7 */
FSM_WR_ENA_HL = 0x5U;
EEPROM_CONFIG_HL = 0x00000002U
| (uint32)((uint32)3U << 16U) ;

/** - Disable write access to flash state machine registers */
FSM_WR_ENA_HL = 0xAU;

/** - Setup flash bank power modes */
flashWREG->FBFALLBACK = 0x00000000U
| (uint32)((uint32)SYS_ACTIVE << 14U) /* BANK 7 */
| (uint32)((uint32)SYS_ACTIVE << 2U) /* BANK 1 */
| (uint32)((uint32)SYS_ACTIVE << 0U); /* BANK 0 */

Can we use like this?

over 5 years ago

0 Someswararao malla over 5 years ago

Intellectual 450 points

0 Someswararao malla over 5 years ago in reply to Someswararao malla

Intellectual 450 points

Please find the attached memory dump

4300.ECC_Event.dat

0 sreenivasan m over 5 years ago in reply to Someswararao malla

Genius 3705 points

Also, as per map file, the address 0x7042 is falling under .cinit section

.cinit 0 00007320 00000100

00007320 000000d8 (.cinit..data.load) [load image, compression = lzss]
000073f8 0000000c (__TI_handler_table)
00007404 00000004 --HOLE-- [fill = ffffffff]
00007408 00000008 (.cinit..bss.load) [load image, compression = zero_init]
00007410 00000010 (__TI_cinit_table)

Do you see any alignment issues here? Could see that error was reported at the end of the flash region which is at 0x7042.

0 sreenivasan m over 5 years ago in reply to sreenivasan m

Genius 3705 points

Can someone look into this share the observations please?

0 Sunil Oak over 5 years ago in reply to sreenivasan m

TI__Mastermind 49120 points

Do you use linker-generated ECC to compute and program the ECC locations for the entire 3MB Flash memory?

0 Someswararao malla over 5 years ago in reply to sreenivasan m

Intellectual 450 points

This is the snippet of generated map file

MEMORY CONFIGURATION

name origin length used unused attr fill
---------------------- -------- --------- -------- -------- ---- --------
VECTORS 00000000 00000020 00000020 00000000 X
FLASH0 00000020 0017ffe0 000073ea 00178bf6 R X
FLASH1 00180000 00180000 00000000 00180000 R X
STACKS 08000000 00001500 00000000 00001500 RW
RAM 08001520 00025ae0 00000644 0002549c RW

SEGMENT ALLOCATION MAP

run origin load origin length init length attrs members
---------- ----------- ---------- ----------- ----- -------
00000000 00000000 00007410 00007410 r-x
00000000 00000000 00000020 00000020 r-x .intvecs
00000020 00000020 00006724 00006724 r-x .text
00006748 00006748 00000bba 00000bba r-- .const
00007304 00007304 0000000c 0000000c r-- .init_array
00007310 00007310 00000100 00000100 r-- .cinit
08001520 08001520 00000644 00000000 rw-
08001520 08001520 000005ea 00000000 rw- .data
08001b0c 08001b0c 00000058 00000000 rw- .bss

We are seeing SEU is being reported for the end of the flash address i.e. 0x7410 and it is being reported multiple times.

we could observe that .init_array is not started with 64-bit alignment address.

After modifying the linker file to make all the sections to be 64-bit aligned, we did not observe any issue.

Can you please explain is there any relation with alignment and SEU.

0 Sunil Oak over 5 years ago in reply to Someswararao malla

TI__Mastermind 49120 points

All accesses to the Flash are 64-bit accesses and an 8-bit ECC is calculated for each 64-bit vale read from the Flash.

So if your last data in Flash memory ends at a 32-bit boundary, whenever this data is accessed the Flash interface module will make a 64-bit access to fill the pipeline with data from the next address. This last prefetch is causing your ECC error.

You can prevent this by aligning all sections in Flash to a 64-bit boundary.

0 Someswararao malla over 5 years ago in reply to Sunil Oak

Intellectual 450 points

Hi Sunil,

We observed SEU exception at 0x7410 which is end of .cinit section.

After updating the linker file to be 8-byte aligned, end of .cinit changed to 0x7418, even this is not a 64-bit aligned.

Can you please let us know what is actual reason for not getting SEU after adding align(8) in linker?

Regards,

Somesh

0 Sunil Oak over 5 years ago in reply to Someswararao malla

TI__Mastermind 49120 points

0x7418 is a 64-bit aligned location. I explained the ECC mechanism on Flash accesses in my previous post.

0 sreenivasan m over 5 years ago in reply to Sunil Oak

Genius 3705 points

Thanks Sunil.

Can cinit section accesses during run time? The reason is that we are getting seu on 0x7410 during run time.

0 sreenivasan m over 5 years ago in reply to sreenivasan m

Genius 3705 points

If possible, can we have a short call on this today? This is bit urgent for us. Thanks for understanding.

0 Sunil Oak over 5 years ago in reply to sreenivasan m

TI__Mastermind 49120 points

Hi Sreenivasan,

Do you still see the single-bit error correction for accesses to the cinit section during execution?

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TMS570LS3137: Single bit Flash errors