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TMS570LC4357: Unexpected EMIF writes access waveforms

Part Number: TMS570LC4357

Hi,

My customer reported unexpected EMIF write access behaviors.
Please see attached excel.
5635.TMS570LC4357_RDWR.xlsx
EMIF is connected to 16bit device and Read and Write accesses are done.
You can see EMIF register setting in “EMIF configuration” sheet.

In “Waveforms” sheet, there are waveforms in six cases.
Top two waveforms are for Read accesses and they are expected.
Middle two waveforms are for Write accesses and it seems write access is followed by other accesses and CS is extended.
Bottom two waveforms are also write accesses and other accesses precede write access.

What causes such behaviors?
Are they expected?

Thanks and regards,
Koichiro Tashiro

  • Hello Koichiro,

    In revA silicon, There is one HW bug: When writing to a EMIF address, the nCS is active for the entire bus transaction while the nWE has 1~2 extra pulses while the nCS is active. 

    In revB silicon, The extra nWE pulses is suppressed during write transactions. However, there was some technical difficulty to shorten the extra duration of the active nCS in addition to removing the extra WE pulses. The nOE is not active during this time. So from a memory access stand point this should be fine. All writes and reads to the memory should be qualified with the valid nWE and nOE.

    For read, not only were we able to remove the extra nOE pulses but also to shorten the nCS as well to improve EMIF performance/bandwidth. Therefore, during read, there is no extra nCS pulses seen in either normal or select strobe mode.

  • Hi QJ,

    Thanks for clarification. This needs to be documented somewhere.
    Customer is wasting the time to debug this behavior.

    Could you add this to Errata or any document?

    Thanks and regards,
    Koichiro Tashiro

  • Hello Koichiro,

    I try to add note to TRM. Thanks