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TMDSCNCD28379D: TMS320F28379D programming

electrocc
Expert 2450 points

Part Number: TMDSCNCD28379D
Other Parts Discussed in Thread: TMS320F28379D,

Hi,

I use a TMS320F28379D on a new board.

Schematics are based on TMDSCNCD28379D schematics for all MCU functions (power supply, support, ADC, XDS100V2 Emulator, Emulator interface).

Power supplies are ok, but when I want to load a program, I cannot connect to the MCU : 

What points can I verify to help me to solve the issue ? Any signals I can check ?

Thank you for your support.

Regards,

  • 0
    TI__Mastermind 30431 points

    Hi,

    Did you replicate the XDS100v2 circuit on your board? If so, have you programmed the XDS100v2 FTDI device with the right firmware?

  • 0 in reply to Gus Martinez
    Expert 2450 points

    Hi Gus,

    Yes, I replicated the XDS100V2 circuit from TMDSCNCD28379D  on my board.
    But I didn't programmed the XDS100v2 FTDI. How do you do ? Do you have a procedure ?

    Is it possible to program only with the USB cable ?

    Thank you.

    Regards

  • 0 in reply to electrocc
    TI__Guru**** 483471 points

    Hello,

    electrocc said:
    But I didn't programmed the XDS100v2 FTDI. How do you do ? Do you have a procedure ?

    Download FT_Prog from:

    https://ftdichip.com/utilities/#ft_prog

    A user's guide for it is also available there.

    I believe you can use the XDS100v2 template from:

    https://software-dl.ti.com/ccs/esd/documents/xdsdebugprobes/emu_xds100.html#template-collection

    Note that you'll likely want to use the standalone one. The F28379D one in the above link is for the XDS100v2 on the LaunchPad only

    Thanks

    ki

  • 0 in reply to Ki
    Expert 2450 points

    Hello Ki,

    I've downloaded FT_Prog and when I scan, I can find the EEPROM : 

    I succeed to program the EEPROM, with initial parameters.

    But what are the settings to set for the standalone mode ? I found nothing on the user's guide and on the FT2232HL datasheet.

    As on the TMDSCNCD28379D board, JTAG port (ADBUS) is connected to the 28379D on my board.
    I used exactly the same schematic than the TMDSCNCD28379D board, except I didn't connect BDBUS0 (EMU_SCI-RX) and BDBUS1 (EMU_SCI-TX). But it doesn't matter because only Port AD (JTAG) is used to program the MCU ?

    Thanks for your support.

    Regards,

  • 0 in reply to electrocc
    TI__Guru**** 483471 points

    In the screenshot you provided, is that before or after you applied the template for the XDS100v2 standalone? I assume it is before, because it doesn't look like the data in the template was applied.

  • 0 in reply to Ki
    Expert 2450 points

    Hello Ki,

    It was before of course I applied a configuration, but I don't think it's the standalone one.

    What is the standalone template please ?

    electrocc said:
    As on the TMDSCNCD28379D board, JTAG port (ADBUS) is connected to the 28379D on my board.
    I used exactly the same schematic than the TMDSCNCD28379D board, except I didn't connect BDBUS0 (EMU_SCI-RX) and BDBUS1 (EMU_SCI-TX). But it doesn't matter because only Port AD (JTAG) is used to program the MCU ?

    Regards,

  • 0 in reply to electrocc
    TI__Guru**** 483471 points
    electrocc said:
    What is the standalone template please ?

    See the following link for a list of all available templates: https://software-dl.ti.com/ccs/esd/documents/xdsdebugprobes/emu_xds100.html#template-collection

  • 0 in reply to Ki
    Expert 2450 points

    Hello Ki,

    So if I load this program in the EEPROM:

    The program is loaded in the EEPROM (I didn't refresh after programming, that's why I have "BLANK DEVICE") .

    But when I try to connect Code Composer, I have this message : 

    What's wrong ? Which points can I verify to solve this issue ?

    Thank you for your support.

    Regards,

  • 0 in reply to electrocc
    TI__Guru**** 483471 points

    It looks like you opened the template but did not program the EEPROM.

    See the steps I did:

    1. Scan for the XDS100v2

    2. Apple the XDS100v2 Template

    3. After the XDS100v2 template has been applied, you should get a message like:

    4. Program the EEPROM

    5. EEPROM should now be programmed (not how "BLANK DEVICE" message is gone and a "Serial Number" is programmed)

    Note that there is a weird issue with FT_Prog where sometimes it doesn't program right and you have to try again. I don't know why, it is some flaky behavior with FT_Prog.

    Hope this works

    ki

  • 0 in reply to Ki
    Expert 2450 points

    Hello Ki,

    This is exactly what I did : 

    The EEPROM seems to be loaded, even if the "Device Output" is not the same than yours.

    But when I try to connect to the MCU with Code Composer, I have an issue: 

    [Start: Texas Instruments XDS100v2 USB Debug Probe_0]

Execute the command:

%ccs_base%/common/uscif/dbgjtag -f %boarddatafile% -rv -o -F inform,logfile=yes -S pathlength -S integrity

[Result]


-----[Print the board config pathname(s)]------------------------------------

C:\Users\perriflo\AppData\Local\TEXASI~1\
    CCS\ti\1\0\BrdDat\testBoard.dat

-----[Print the reset-command software log-file]-----------------------------

This utility has selected a 100- or 510-class product.
This utility will load the adapter 'jioserdesusb.dll'.
The library build date was 'Nov 21 2018'.
The library build time was '00:08:45'.
The library package version is '8.0.903.2'.
The library component version is '35.35.0.0'.
The controller does not use a programmable FPGA.
The controller has a version number of '4' (0x00000004).
The controller has an insertion length of '0' (0x00000000).
This utility will attempt to reset the controller.
This utility has successfully reset the controller.

-----[Print the reset-command hardware log-file]-----------------------------

The scan-path will be reset by toggling the JTAG TRST signal.
The controller is the FTDI FT2232 with USB interface.
The link from controller to target is direct (without cable).
The software is configured for FTDI FT2232 features.
The controller cannot monitor the value on the EMU[0] pin.
The controller cannot monitor the value on the EMU[1] pin.
The controller cannot control the timing on output pins.
The controller cannot control the timing on input pins.
The scan-path link-delay has been set to exactly '0' (0x0000).

-----[The log-file for the JTAG TCLK output generated from the PLL]----------

There is no hardware for programming the JTAG TCLK frequency.

-----[Measure the source and frequency of the final JTAG TCLKR input]--------

There is no hardware for measuring the JTAG TCLK frequency.

-----[Perform the standard path-length test on the JTAG IR and DR]-----------

This path-length test uses blocks of 64 32-bit words.

The test for the JTAG IR instruction path-length failed.
The JTAG IR instruction scan-path is stuck-at-ones.

The test for the JTAG DR bypass path-length failed.
The JTAG DR bypass scan-path is stuck-at-ones.

-----[Perform the Integrity scan-test on the JTAG IR]------------------------

This test will use blocks of 64 32-bit words.
This test will be applied just once.

Do a test using 0xFFFFFFFF.
Scan tests: 1, skipped: 0, failed: 0
Do a test using 0x00000000.
Test 2 Word 0: scanned out 0x00000000 and scanned in 0xFFFFFFFF.
Test 2 Word 1: scanned out 0x00000000 and scanned in 0xFFFFFFFF.
Test 2 Word 2: scanned out 0x00000000 and scanned in 0xFFFFFFFF.
Test 2 Word 3: scanned out 0x00000000 and scanned in 0xFFFFFFFF.
Test 2 Word 4: scanned out 0x00000000 and scanned in 0xFFFFFFFF.
Test 2 Word 5: scanned out 0x00000000 and scanned in 0xFFFFFFFF.
Test 2 Word 6: scanned out 0x00000000 and scanned in 0xFFFFFFFF.
Test 2 Word 7: scanned out 0x00000000 and scanned in 0xFFFFFFFF.
The details of the first 8 errors have been provided.
The utility will now report only the count of failed tests.
Scan tests: 2, skipped: 0, failed: 1
Do a test using 0xFE03E0E2.
Scan tests: 3, skipped: 0, failed: 2
Do a test using 0x01FC1F1D.
Scan tests: 4, skipped: 0, failed: 3
Do a test using 0x5533CCAA.
Scan tests: 5, skipped: 0, failed: 4
Do a test using 0xAACC3355.
Scan tests: 6, skipped: 0, failed: 5
Some of the values were corrupted - 83.3 percent.

The JTAG IR Integrity scan-test has failed.

-----[Perform the Integrity scan-test on the JTAG DR]------------------------

This test will use blocks of 64 32-bit words.
This test will be applied just once.

Do a test using 0xFFFFFFFF.
Scan tests: 1, skipped: 0, failed: 0
Do a test using 0x00000000.
Test 2 Word 0: scanned out 0x00000000 and scanned in 0xFFFFFFFF.
Test 2 Word 1: scanned out 0x00000000 and scanned in 0xFFFFFFFF.
Test 2 Word 2: scanned out 0x00000000 and scanned in 0xFFFFFFFF.
Test 2 Word 3: scanned out 0x00000000 and scanned in 0xFFFFFFFF.
Test 2 Word 4: scanned out 0x00000000 and scanned in 0xFFFFFFFF.
Test 2 Word 5: scanned out 0x00000000 and scanned in 0xFFFFFFFF.
Test 2 Word 6: scanned out 0x00000000 and scanned in 0xFFFFFFFF.
Test 2 Word 7: scanned out 0x00000000 and scanned in 0xFFFFFFFF.
The details of the first 8 errors have been provided.
The utility will now report only the count of failed tests.
Scan tests: 2, skipped: 0, failed: 1
Do a test using 0xFE03E0E2.
Scan tests: 3, skipped: 0, failed: 2
Do a test using 0x01FC1F1D.
Scan tests: 4, skipped: 0, failed: 3
Do a test using 0x5533CCAA.
Scan tests: 5, skipped: 0, failed: 4
Do a test using 0xAACC3355.
Scan tests: 6, skipped: 0, failed: 5
Some of the values were corrupted - 83.3 percent.

The JTAG DR Integrity scan-test has failed.

[End: Texas Instruments XDS100v2 USB Debug Probe_0]

    Which signals can I check ?

    Which points can I verify to solve this issue ?

    Thank you for your support.

    Regards,

  • 0 in reply to electrocc
    TI__Guru**** 483471 points
    electrocc said:
    The EEPROM seems to be loaded, even if the "Device Output" is not the same than yours.

    Yes, this looks good

    The XDS100v2 has been programmed and detected by your system and CCS. This part is now good.

    But your latest error is due to the JTAG connectivity test failing:

    https://software-dl.ti.com/ccs/esd/documents/ccs_debugging_jtag_connectivity_issues.html#invalid-data-read-back

    This is a low level connection failure, most often due to poor hardware connections or poor signal integrity on the JTAG scan chain. Please see the above link for more details on the error and suggestions on how to resolve.

    Thanks

    ki

  • 0 in reply to Ki
    Expert 2450 points

    Hello Ki,

    Thanks for your feedback. How do you know that the XDS100v2 is detected by CCS ? Is it mentioned in the report ?

    I'll try to scope all JTAG signals ; what should JTAG signals look like?

    - TRSTN : high or low level ?
    - TMS :  high or low level ?

    How can you set the bootmode to JTAG ? Can it be the issue ?

    Thank you for your support.

    Regards,

  • 0 in reply to electrocc
    TI__Guru**** 483471 points
    electrocc said:
    How do you know that the XDS100v2 is detected by CCS ? Is it mentioned in the report ?

    Yes. Your "Test Connection" attempted would have failed immediately if CCS was unable to detect a working XDS100v2. Your failure was when CCS was reading back bits it circulated on the JTAG scan chain. At this point, CCS has established a valid connection with the XDS100v2.

    electrocc said:
    I'll try to scope all JTAG signals ; what should JTAG signals look like?

    Please refer to this document:

    https://software-dl.ti.com/ccs/esd/documents/xdsdebugprobes/emu_xds_target_connection_guide.html

    Thanks

    ki

  • 0 in reply to Ki
    Expert 2450 points

    Hello Ki,

    Please find different JTAG signals scoped directly on the MCU chip pins when I tested the JTAG connection.

    MCU_TCK : 

    MCU_TDI : 

    MCU_TDO : 

    MCU_TMS : 

    MCU_TRSTN : 

    I've read possible cause : 

    If the data read back is all ones (0xFFFFFFFF), it is possible that one of the JTAG lines has a short to VCC.

    I don't think I've a short to VCC.

    If using an isolated JTAG debug probe, it is possible that both scenarios may happen if the target board or device is powered down. In this case, make sure power is properly applied across the system.
Most of the F28x development kits return 0xFFFFFFFF if the device section of the kit is powered down (if the kit has an isolated JTAG), if the jumper settings disable JTAG access or if the bootmode is set to anything other than JTAG. Please carefully review the documentation of your kit.

    All power supplies on the board looks correct (F28379 power supplies and JTAG power supplies)

    Certain devices such as F28x suggest a resistor to pull the TRST pin low. However, if the resistor is too small this error may manifest itself. This is reported in this e2e forum post.

    TRST high signal is 3V3, so I don't think it's could be the cause of the issue.

    What can I do to solve the issue ? Any point I can verify 

    Do I have to modify the Advanced Connection Properties ?

    How can I be sure that my MCU is working properly ? What must be the value of the /XRS pin ?

    Thanks for your support.

    Regards,

  • 0 in reply to electrocc
    TI__Guru**** 483471 points
    electrocc said:

    What can I do to solve the issue ? Any point I can verify 

    Do I have to modify the Advanced Connection Properties ?

    Did you try lowering the JTAG TCLK frequency?

  • 0 in reply to Ki
    Expert 2450 points

    Hello Ki,

    Yes I try lowering JTAG TCLK frequency (100kHz, 50kHz) and increasing frequency ( 5Mhz).

    Nothing change, I have always the same error message : 

    [Start: Texas Instruments XDS100v2 USB Debug Probe_0]

Execute the command:

%ccs_base%/common/uscif/dbgjtag -f %boarddatafile% -rv -o -F inform,logfile=yes -S pathlength -S integrity

[Result]


-----[Print the board config pathname(s)]------------------------------------

C:\Users\perriflo\AppData\Local\TEXASI~1\
    CCS\ti\1\0\BrdDat\testBoard.dat

-----[Print the reset-command software log-file]-----------------------------

This utility has selected a 100- or 510-class product.
This utility will load the adapter 'jioserdesusb.dll'.
The library build date was 'Nov 21 2018'.
The library build time was '00:08:45'.
The library package version is '8.0.903.2'.
The library component version is '35.35.0.0'.
The controller does not use a programmable FPGA.
The controller has a version number of '4' (0x00000004).
The controller has an insertion length of '0' (0x00000000).
This utility will attempt to reset the controller.
This utility has successfully reset the controller.

-----[Print the reset-command hardware log-file]-----------------------------

The scan-path will be reset by toggling the JTAG TRST signal.
The controller is the FTDI FT2232 with USB interface.
The link from controller to target is direct (without cable).
The software is configured for FTDI FT2232 features.
The controller cannot monitor the value on the EMU[0] pin.
The controller cannot monitor the value on the EMU[1] pin.
The controller cannot control the timing on output pins.
The controller cannot control the timing on input pins.
The scan-path link-delay has been set to exactly '0' (0x0000).

-----[The log-file for the JTAG TCLK output generated from the PLL]----------

There is no hardware for programming the JTAG TCLK frequency.

-----[Measure the source and frequency of the final JTAG TCLKR input]--------

There is no hardware for measuring the JTAG TCLK frequency.

-----[Perform the standard path-length test on the JTAG IR and DR]-----------

This path-length test uses blocks of 64 32-bit words.

The test for the JTAG IR instruction path-length failed.
The JTAG IR instruction scan-path is stuck-at-ones.

The test for the JTAG DR bypass path-length failed.
The JTAG DR bypass scan-path is stuck-at-ones.

-----[Perform the Integrity scan-test on the JTAG IR]------------------------

This test will use blocks of 64 32-bit words.
This test will be applied just once.

Do a test using 0xFFFFFFFF.
Scan tests: 1, skipped: 0, failed: 0
Do a test using 0x00000000.
Test 2 Word 0: scanned out 0x00000000 and scanned in 0xFFFFFFFF.
Test 2 Word 1: scanned out 0x00000000 and scanned in 0xFFFFFFFF.
Test 2 Word 2: scanned out 0x00000000 and scanned in 0xFFFFFFFF.
Test 2 Word 3: scanned out 0x00000000 and scanned in 0xFFFFFFFF.
Test 2 Word 4: scanned out 0x00000000 and scanned in 0xFFFFFFFF.
Test 2 Word 5: scanned out 0x00000000 and scanned in 0xFFFFFFFF.
Test 2 Word 6: scanned out 0x00000000 and scanned in 0xFFFFFFFF.
Test 2 Word 7: scanned out 0x00000000 and scanned in 0xFFFFFFFF.
The details of the first 8 errors have been provided.
The utility will now report only the count of failed tests.
Scan tests: 2, skipped: 0, failed: 1
Do a test using 0xFE03E0E2.
Scan tests: 3, skipped: 0, failed: 2
Do a test using 0x01FC1F1D.
Scan tests: 4, skipped: 0, failed: 3
Do a test using 0x5533CCAA.
Scan tests: 5, skipped: 0, failed: 4
Do a test using 0xAACC3355.
Scan tests: 6, skipped: 0, failed: 5
Some of the values were corrupted - 83.3 percent.

The JTAG IR Integrity scan-test has failed.

-----[Perform the Integrity scan-test on the JTAG DR]------------------------

This test will use blocks of 64 32-bit words.
This test will be applied just once.

Do a test using 0xFFFFFFFF.
Scan tests: 1, skipped: 0, failed: 0
Do a test using 0x00000000.
Test 2 Word 0: scanned out 0x00000000 and scanned in 0xFFFFFFFF.
Test 2 Word 1: scanned out 0x00000000 and scanned in 0xFFFFFFFF.
Test 2 Word 2: scanned out 0x00000000 and scanned in 0xFFFFFFFF.
Test 2 Word 3: scanned out 0x00000000 and scanned in 0xFFFFFFFF.
Test 2 Word 4: scanned out 0x00000000 and scanned in 0xFFFFFFFF.
Test 2 Word 5: scanned out 0x00000000 and scanned in 0xFFFFFFFF.
Test 2 Word 6: scanned out 0x00000000 and scanned in 0xFFFFFFFF.
Test 2 Word 7: scanned out 0x00000000 and scanned in 0xFFFFFFFF.
The details of the first 8 errors have been provided.
The utility will now report only the count of failed tests.
Scan tests: 2, skipped: 0, failed: 1
Do a test using 0xFE03E0E2.
Scan tests: 3, skipped: 0, failed: 2
Do a test using 0x01FC1F1D.
Scan tests: 4, skipped: 0, failed: 3
Do a test using 0x5533CCAA.
Scan tests: 5, skipped: 0, failed: 4
Do a test using 0xAACC3355.
Scan tests: 6, skipped: 0, failed: 5
Some of the values were corrupted - 83.3 percent.

The JTAG DR Integrity scan-test has failed.

[End: Texas Instruments XDS100v2 USB Debug Probe_0]

    Regards,

  • 0 in reply to Ki
    Expert 2450 points

    Hello Ki,

    Do you have any idea to help me to solve this issue ?

    Any points I can verify, measures I can take ?

    Thank you for your support.

    Regards,

  • 0 in reply to electrocc
    TI__Guru**** 483471 points

    Sorry, but I cannot think of any more suggestions. This is a bit beyond my area of expertise. I will reach out to some of my colleagues who have more hardware expertise and will keep you posted of any updates I get

    ki

  • 0 in reply to Ki
    TI__Guru**** 483471 points

    We are still investigating the issue. Sorry for the delay

    ki

  • 0 in reply to Ki
    TI__Mastermind 30431 points

    Would you mind sharing your schematics in a private email? I can take a look and at the JTAG section to see if anything stands out.

  • +1 in reply to Gus Martinez
    TI__Mastermind 30431 points

    , thanks for sharing the schematics separately. As discussed in one-on-one thread, there is an issue with the connection of the TDO pin across the isolation device. This would be consistent with the scan-test failure. If possible, remove the isolation device and short the TDO traces across the isolation boundary for debug.

  • 0 in reply to Gus Martinez
    Expert 2450 points

    Hi Gus,

    Yes, it was the issue. Problem is solved now.

    Thank you very much for your support.