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C2000WARE: Error/warning: Creation of output section without "SECTION" definition

Joel Holland
Intellectual 765 points

Part Number: C2000WARE

Hi,

I am getting an issue in C2000 program, regarding creation of output sections without section definitions


**** Build of configuration CPU1_RAM for project HV_MPM_CPU1 ****

"C:\\ti\\ccs1020\\ccs\\utils\\bin\\gmake" -k -j 4 all -O

Building target: "HV_MPM_CPU1.out"
Invoking: C2000 Linker
"C:/ti/ccs1020/ccs/tools/compiler/ti-cgt-c2000_20.2.2.LTS/bin/cl2000" -v28 -ml -mt --cla_support=cla1 --float_support=fpu32 --tmu_support=tmu0 --vcu_support=vcu2 -Ooff --define=_DUAL_HEADERS --define=DEBUG --define=CPU1 --diag_suppress=10063 --diag_warning=225 --diag_wrap=off --display_error_number --abi=eabi -z -m"HV_MPM_CPU1.map" --stack_size=0x100 --warn_sections -i"C:/ti/ccs1020/ccs/tools/compiler/ti-cgt-c2000_20.2.2.LTS/lib" -i"C:/ti/ccs1020/ccs/tools/compiler/ti-cgt-c2000_20.2.2.LTS/include" --reread_libs --diag_wrap=off --display_error_number --xml_link_info="HV_MPM_CPU1_linkInfo.xml" --entry_point=code_start --rom_model -o "HV_MPM_CPU1.out" "./CLA_Fly.obj" "./MPM_CPU1.obj" "./device/F2837xD_CodeStartBranch.obj" "./device/device.obj" "./libraries/DCL/DCL_DF11_L1.obj" "./libraries/DCL/DCL_DF22_L2L3.obj" "./libraries/DCL/DCL_clamp_L1.obj" "../2837xD_RAM_lnk_cpu1.cmd" "../F2837xD_Headers_nonBIOS_cpu1.cmd" "C:/ti/c2000/C2000Ware_3_04_00_00/driverlib/f2837xd/driverlib/ccs/Debug/driverlib.lib" -llibc.a
<Linking>
warning #10440-D: creating output section ".bss" without a SECTIONS specification. For additional information on this section, please see the 'C2000 Migration from COFF to EABI' guide at software-dl.ti.com/.../C2000_c28x_migration_from_coff_to_eabi.html
warning #10440-D: creating output section ".const" without a SECTIONS specification. For additional information on this section, please see the 'C2000 Migration from COFF to EABI' guide at software-dl.ti.com/.../C2000_c28x_migration_from_coff_to_eabi.html
warning #10440-D: creating output section ".sysmem" without a SECTIONS specification. For additional information on this section, please see the 'C2000 Migration from COFF to EABI' guide at software-dl.ti.com/.../C2000_c28x_migration_from_coff_to_eabi.html
warning #10440-D: creating output section ".init_array" without a SECTIONS specification. For additional information on this section, please see the 'C2000 Migration from COFF to EABI' guide at software-dl.ti.com/.../C2000_c28x_migration_from_coff_to_eabi.html
warning #10247-D: creating output section ".data" without a SECTIONS specification

undefined first referenced
symbol in file
--------- ----------------
AdcaRegs ./MPM_CPU1.obj
AdcaResultRegs ./MPM_CPU1.obj
AdcbRegs ./MPM_CPU1.obj
AdcbResultRegs ./MPM_CPU1.obj
AdccRegs ./MPM_CPU1.obj
AdccResultRegs ./MPM_CPU1.obj
AuxCPU_ISR ./MPM_CPU1.obj
Cla1Regs ./MPM_CPU1.obj
Cla1Task1 ./MPM_CPU1.obj
Cla1Task2 ./MPM_CPU1.obj
Cla1Task3 ./MPM_CPU1.obj
Cla1Task4 ./MPM_CPU1.obj
Cla1Task5 ./MPM_CPU1.obj
Cla1Task6 ./MPM_CPU1.obj
Cla1Task7 ./MPM_CPU1.obj
Cla1Task8 ./MPM_CPU1.obj
ClkCfgRegs ./MPM_CPU1.obj
Cmpss1Regs ./MPM_CPU1.obj
Cmpss2Regs ./MPM_CPU1.obj
Cmpss3Regs ./MPM_CPU1.obj
Cmpss5Regs ./MPM_CPU1.obj
Cmpss6Regs ./MPM_CPU1.obj
CpuSysRegs ./MPM_CPU1.obj
CpuTimer0Regs ./MPM_CPU1.obj
DacaRegs ./MPM_CPU1.obj
DacbRegs ./MPM_CPU1.obj
DaccRegs ./MPM_CPU1.obj
DmaClaSrcSelRegs ./MPM_CPU1.obj
EPwm1Regs ./MPM_CPU1.obj
EPwm4Regs ./MPM_CPU1.obj
EPwmXbarRegs ./MPM_CPU1.obj
F28x_usDelay ./MPM_CPU1.obj
GpioCtrlRegs ./MPM_CPU1.obj
GpioDataRegs ./MPM_CPU1.obj
InitEPwm1Gpio ./MPM_CPU1.obj
InitEPwm4Gpio ./MPM_CPU1.obj
InitGpio ./MPM_CPU1.obj
InitInputXbar ./MPM_CPU1.obj
InitPieCtrl ./MPM_CPU1.obj
InitPieVectTable ./MPM_CPU1.obj
InitSysCtrl ./MPM_CPU1.obj
IpcRegs ./MPM_CPU1.obj
MemCfgRegs ./MPM_CPU1.obj
PieCtrlRegs ./MPM_CPU1.obj
PieVectTable ./MPM_CPU1.obj
SFO ./MPM_CPU1.obj
main C:\ti\ccs1020\ccs\tools\compiler\ti-cgt-c2000_20.2.2.LTS\lib\rts2800_fpu32_eabi.lib<args_main.c.obj>

error #10234-D: unresolved symbols remain
error #10010: errors encountered during linking; "HV_MPM_CPU1.out" not built

>> Compilation failure
makefile:153: recipe for target 'HV_MPM_CPU1.out' failed
gmake[1]: *** [HV_MPM_CPU1.out] Error 1
makefile:149: recipe for target 'all' failed
gmake: *** [all] Error 2

**** Build Finished ****

This is mostly confusing me because when searching the default linker file Headers_nonBIOS and the default RAM linker file (shown below):

/* JMH modified for LV board */

#ifdef CLA_C
CLA_SCRATCHPAD_SIZE = 0x200; /* original value = 0x100 */
--undef_sym=__cla_scratchpad_end
--undef_sym=__cla_scratchpad_start
#endif

-heap 0x2000 /* extend esysmem to 8k */

MEMORY
{
PAGE 0 : /* Program Memory */
/* BEGIN is used for the "boot to SARAM" bootloader mode */

BEGIN : origin = 0x000000, length = 0x000002
RAMM0 : origin = 0x000122, length = 0x0002DE
/*
RAMLS4 : origin = 0x00A000, length = 0x000800
RAMLS5 : origin = 0x00A800, length = 0x000800
*/
RAMLS4_5 : origin = 0x00A000, length = 0x001000 /* 4k RAM for CLA1 */
RESET : origin = 0x3FFFC0, length = 0x000002
FLASHB : origin = 0x082000, length = 0x002000 /* on-chip Flash, use for initialisation functions */
FLASHC : origin = 0x084000, length = 0x002000 /* on-chip Flash */
RAMGS0_3 : origin = 0x00C000, length = 0x004000 /* 16k (GS0-GS3) for C28x(cpu1) .text */
RAMGS4 : origin = 0x010000, length = 0x001000

PAGE 1 : /* Data Memory */

BOOT_RSVD : origin = 0x000002, length = 0x000120 /* Part of M0, BOOT rom will use this for stack */
RAMM1 : origin = 0x000400, length = 0x000400 /* on-chip RAM block M1 */
RAMD0_D1 : origin = 0x00B000, length = 0x001000 /* Expand .ebss for more global variables */

RAMLS0 : origin = 0x008000, length = 0x000800
RAMLS1 : origin = 0x008800, length = 0x000800
RAMLS2 : origin = 0x009000, length = 0x000800
RAMLS3 : origin = 0x009800, length = 0x000800


RAMGS5 : origin = 0x011000, length = 0x001000
RAMGS6 : origin = 0x012000, length = 0x001000
RAMGS7 : origin = 0x013000, length = 0x001000
RAMGS8 : origin = 0x014000, length = 0x001000
RAMGS9 : origin = 0x015000, length = 0x001000
RAMGS10_11 : origin = 0x016000, length = 0x002000 /* 8k heap */
RAMGS12 : origin = 0x018000, length = 0x001000
RAMGS13 : origin = 0x019000, length = 0x001000
RAMGS14 : origin = 0x01A000, length = 0x001000
RAMGS15 : origin = 0x01B000, length = 0x001000

CPU2TOCPU1RAM : origin = 0x03F800, length = 0x000400
CPU1TOCPU2RAM : origin = 0x03FC00, length = 0x000400

CLA1_MSGRAMLOW : origin = 0x001480, length = 0x000080
CLA1_MSGRAMHIGH : origin = 0x001500, length = 0x000080
}


SECTIONS
{
codestart : > BEGIN, PAGE = 0
ramfuncs : > RAMM0 PAGE = 0
.text : > RAMGS0_3 PAGE = 0
/* .sect "codeA" : > FLASHB PAGE = 0, ALIGN(64) /*to locate some functions elsewhere */
/* .sect "codeA" : > RAMGS4 PAGE = 0 /*to locate some functions elsewhere */
.cinit : > RAMM0, PAGE = 0
.pinit : > RAMM0, PAGE = 0
.switch : > RAMM0, PAGE = 0
.reset : > RESET, PAGE = 0, TYPE = DSECT /* not used, */

.stack : > RAMM1, PAGE = 1
.ebss : > RAMD0_D1, PAGE = 1

.econst : > RAMD0_D1, PAGE = 1
.esysmem : > RAMGS10_11 PAGE = 1 /* contains heap */

/* CLA sections */
// I believe these sections are user-defined and have been modified by Dave
Cla1Prog : > RAMLS4_5, PAGE = 0
CLADataLS0 : > RAMLS0, PAGE = 1
CLADataLS1 : > RAMLS1, PAGE = 1

Cla1ToCpuMsgRAM : > CLA1_MSGRAMLOW, PAGE = 1
CpuToCla1MsgRAM : > CLA1_MSGRAMHIGH, PAGE = 1

Cpu1ToCpu2RAM : > CPU1TOCPU2RAM, PAGE = 1
Cpu2ToCpu1RAM : > CPU2TOCPU1RAM, PAGE = 1

/* Digital Controller Library functions */
dclfuncs : > RAMLS4_5, PAGE = 0
dcl32funcs : > RAMLS4_5, PAGE = 0

ramfuncs : > RAMLS4_5, PAGE = 0
LOAD_START(_RamfuncsLoadStart),
LOAD_END(_RamfuncsLoadEnd),
RUN_START(_RamfuncsRunStart),
RUN_SIZE(_RamfuncsRUNSize)

#ifdef CLA_C

CLAscratch :
{ *.obj(CLAscratch)
. += CLA_SCRATCHPAD_SIZE;
*.obj(CLAscratch_end) } > RAMLS1, PAGE = 1

.scratchpad : > RAMLS1, PAGE = 1
.bss_cla : > RAMLS1, PAGE = 1
.const_cla : > RAMLS1, PAGE = 1
#endif


/* The following section definitions are required when using the IPC API Drivers */
GROUP : > CPU1TOCPU2RAM, PAGE = 1
{
PUTBUFFER
PUTWRITEIDX
GETREADIDX
}

GROUP : > CPU2TOCPU1RAM, PAGE = 1
{
GETBUFFER : TYPE = DSECT
GETWRITEIDX : TYPE = DSECT
PUTREADIDX : TYPE = DSECT
}

/* The following section definition are for SDFM examples */
/*
Filter1_RegsFile : > RAMGS1, PAGE = 1, fill=0x1111
Filter2_RegsFile : > RAMGS2, PAGE = 1, fill=0x2222
Filter3_RegsFile : > RAMGS3, PAGE = 1, fill=0x3333
Filter4_RegsFile : > RAMGS4, PAGE = 1, fill=0x4444
Difference_RegsFile : >RAMGS5, PAGE = 1, fill=0x3333
*/

}

There is no mention of any of these sections in the file. So I am unsure if they are causing an error from an external file elsewhere in the project.

Also, these are warnings and not errors, so should they be stopping me from compiling the project, anyway?

Best regards,

Joel

  • 0
    Intellectual 765 points

    Hello,

    I used a DCL example which included the above sections with definitions and added them to my linker file, and placed them in the CPU RAM as follows: 

    /* JMH modified for LV board */

    #ifdef CLA_C
    CLA_SCRATCHPAD_SIZE = 0x200; /* original value = 0x100 */
    --undef_sym=__cla_scratchpad_end
    --undef_sym=__cla_scratchpad_start
    #endif

    -heap 0x2000 /* extend esysmem to 8k */

    MEMORY
    {
    PAGE 0 : /* Program Memory */
    /* BEGIN is used for the "boot to SARAM" bootloader mode */

    BEGIN : origin = 0x000000, length = 0x000002
    RAMM0 : origin = 0x000122, length = 0x0002DE
    /*
    RAMLS4 : origin = 0x00A000, length = 0x000800
    RAMLS5 : origin = 0x00A800, length = 0x000800
    */
    RAMLS4_5 : origin = 0x00A000, length = 0x001000 /* 4k RAM for CLA1 */
    RESET : origin = 0x3FFFC0, length = 0x000002
    FLASHB : origin = 0x082000, length = 0x002000 /* on-chip Flash, use for initialisation functions */
    FLASHC : origin = 0x084000, length = 0x002000 /* on-chip Flash */
    RAMGS0_3 : origin = 0x00C000, length = 0x004000 /* 16k (GS0-GS3) for C28x(cpu1) .text */
    RAMGS4 : origin = 0x010000, length = 0x001000

    PAGE 1 : /* Data Memory */

    BOOT_RSVD : origin = 0x000002, length = 0x000120 /* Part of M0, BOOT rom will use this for stack */
    RAMM1 : origin = 0x000400, length = 0x000400 /* on-chip RAM block M1 */
    RAMD0_D1 : origin = 0x00B000, length = 0x001000 /* Expand .ebss for more global variables */

    RAMLS0 : origin = 0x008000, length = 0x000800
    RAMLS1 : origin = 0x008800, length = 0x000800
    RAMLS2 : origin = 0x009000, length = 0x000800
    RAMLS3 : origin = 0x009800, length = 0x000800


    RAMGS5 : origin = 0x011000, length = 0x001000
    RAMGS6 : origin = 0x012000, length = 0x001000
    RAMGS7 : origin = 0x013000, length = 0x001000
    RAMGS8 : origin = 0x014000, length = 0x001000
    RAMGS9 : origin = 0x015000, length = 0x001000
    RAMGS10_11 : origin = 0x016000, length = 0x002000 /* 8k heap */
    RAMGS12 : origin = 0x018000, length = 0x001000
    RAMGS13 : origin = 0x019000, length = 0x001000
    RAMGS14 : origin = 0x01A000, length = 0x001000
    RAMGS15 : origin = 0x01B000, length = 0x001000

    CPU2TOCPU1RAM : origin = 0x03F800, length = 0x000400
    CPU1TOCPU2RAM : origin = 0x03FC00, length = 0x000400

    CLA1_MSGRAMLOW : origin = 0x001480, length = 0x000080
    CLA1_MSGRAMHIGH : origin = 0x001500, length = 0x000080
    }


    SECTIONS
    {
    codestart : > BEGIN, PAGE = 0
    ramfuncs : > RAMM0 PAGE = 0
    .text : > RAMGS0_3 PAGE = 0
    /* .sect "codeA" : > FLASHB PAGE = 0, ALIGN(64) /*to locate some functions elsewhere */
    /* .sect "codeA" : > RAMGS4 PAGE = 0 /*to locate some functions elsewhere */
    .cinit : > RAMM0, PAGE = 0
    .pinit : > RAMM0, PAGE = 0
    .switch : > RAMM0, PAGE = 0
    .reset : > RESET, PAGE = 0, TYPE = DSECT /* not used, */

    .stack : > RAMM1, PAGE = 1
    .ebss : > RAMD0_D1, PAGE = 1

    .econst : > RAMD0_D1, PAGE = 1
    .esysmem : > RAMGS10_11 PAGE = 1 /* contains heap */

    // Added by JMH from DCL example linker file
    // try RAMM1 memory block for now, since RAML4_5 is dedicated to the CLA
    // Check the available memory above, and make sure you get the correct
    // data section AND the page that this memory is contained
    .data : > RAMGS5, PAGE = 1 /* constant data */
    .init_array : > RAMGS5, PAGE = 1 /* for EABI */


    /* 16-Bit data sections */
    .const : > RAMM0, PAGE = 0 /* near constants */
    .bss : > RAMM0, PAGE = 0 /* near variables */
    RUN_START(_bss_start),
    RUN_SIZE(_bss_size)

    .sysmem : > RAMM0, PAGE = 0 /* near dynamic memory */

    /* CLA sections */
    // I believe these sections are user-defined and have been modified by Dave
    Cla1Prog : > RAMLS4_5, PAGE = 0
    CLADataLS0 : > RAMLS0, PAGE = 1
    CLADataLS1 : > RAMLS1, PAGE = 1

    Cla1ToCpuMsgRAM : > CLA1_MSGRAMLOW, PAGE = 1
    CpuToCla1MsgRAM : > CLA1_MSGRAMHIGH, PAGE = 1

    Cpu1ToCpu2RAM : > CPU1TOCPU2RAM, PAGE = 1
    Cpu2ToCpu1RAM : > CPU2TOCPU1RAM, PAGE = 1

    /* Digital Controller Library functions */
    dclfuncs : > RAMLS4_5, PAGE = 0
    dcl32funcs : > RAMLS4_5, PAGE = 0

    ramfuncs : > RAMLS4_5, PAGE = 0
    LOAD_START(_RamfuncsLoadStart),
    LOAD_END(_RamfuncsLoadEnd),
    RUN_START(_RamfuncsRunStart),
    RUN_SIZE(_RamfuncsRUNSize)

    #ifdef CLA_C

    CLAscratch :
    { *.obj(CLAscratch)
    . += CLA_SCRATCHPAD_SIZE;
    *.obj(CLAscratch_end) } > RAMLS1, PAGE = 1

    .scratchpad : > RAMLS1, PAGE = 1
    .bss_cla : > RAMLS1, PAGE = 1
    .const_cla : > RAMLS1, PAGE = 1
    #endif


    /* The following section definitions are required when using the IPC API Drivers */
    GROUP : > CPU1TOCPU2RAM, PAGE = 1
    {
    PUTBUFFER
    PUTWRITEIDX
    GETREADIDX
    }

    GROUP : > CPU2TOCPU1RAM, PAGE = 1
    {
    GETBUFFER : TYPE = DSECT
    GETWRITEIDX : TYPE = DSECT
    PUTREADIDX : TYPE = DSECT
    }

    /* The following section definition are for SDFM examples */
    /*
    Filter1_RegsFile : > RAMGS1, PAGE = 1, fill=0x1111
    Filter2_RegsFile : > RAMGS2, PAGE = 1, fill=0x2222
    Filter3_RegsFile : > RAMGS3, PAGE = 1, fill=0x3333
    Filter4_RegsFile : > RAMGS4, PAGE = 1, fill=0x4444
    Difference_RegsFile : >RAMGS5, PAGE = 1, fill=0x3333
    */

    }

    /*
    //===========================================================================
    // End of file.
    //===========================================================================
    */

    This removes the warnings, but I still cannot get the file to compile:


    **** Build of configuration CPU1_RAM for project HV_MPM_CPU1 ****

    "C:\\ti\\ccs1020\\ccs\\utils\\bin\\gmake" -k -j 4 all -O

    Building target: "HV_MPM_CPU1.out"
    Invoking: C2000 Linker
    "C:/ti/ccs1020/ccs/tools/compiler/ti-cgt-c2000_20.2.2.LTS/bin/cl2000" -v28 -ml -mt --cla_support=cla1 --float_support=fpu32 --tmu_support=tmu0 --vcu_support=vcu2 -Ooff --define=_DUAL_HEADERS --define=DEBUG --define=CPU1 --diag_suppress=10063 --diag_warning=225 --diag_wrap=off --display_error_number --abi=eabi -z -m"HV_MPM_CPU1.map" --stack_size=0x100 --warn_sections -i"C:/ti/ccs1020/ccs/tools/compiler/ti-cgt-c2000_20.2.2.LTS/lib" -i"C:/ti/ccs1020/ccs/tools/compiler/ti-cgt-c2000_20.2.2.LTS/include" --reread_libs --diag_wrap=off --display_error_number --xml_link_info="HV_MPM_CPU1_linkInfo.xml" --entry_point=code_start --rom_model -o "HV_MPM_CPU1.out" "./CLA_Fly.obj" "./MPM_CPU1.obj" "./device/F2837xD_CodeStartBranch.obj" "./device/device.obj" "./libraries/DCL/DCL_DF11_L1.obj" "./libraries/DCL/DCL_DF22_L2L3.obj" "./libraries/DCL/DCL_clamp_L1.obj" "../2837xD_RAM_lnk_cpu1.cmd" "../F2837xD_Headers_nonBIOS_cpu1.cmd" "C:/ti/c2000/C2000Ware_3_04_00_00/driverlib/f2837xd/driverlib/ccs/Debug/driverlib.lib" -llibc.a
    <Linking>

    undefined first referenced
    symbol in file
    --------- ----------------
    AdcaRegs ./MPM_CPU1.obj
    AdcaResultRegs ./MPM_CPU1.obj
    AdcbRegs ./MPM_CPU1.obj
    AdcbResultRegs ./MPM_CPU1.obj
    AdccRegs ./MPM_CPU1.obj
    AdccResultRegs ./MPM_CPU1.obj
    AuxCPU_ISR ./MPM_CPU1.obj
    Cla1Regs ./MPM_CPU1.obj
    Cla1Task1 ./MPM_CPU1.obj
    Cla1Task2 ./MPM_CPU1.obj
    Cla1Task3 ./MPM_CPU1.obj
    Cla1Task4 ./MPM_CPU1.obj
    Cla1Task5 ./MPM_CPU1.obj
    Cla1Task6 ./MPM_CPU1.obj
    Cla1Task7 ./MPM_CPU1.obj
    Cla1Task8 ./MPM_CPU1.obj
    ClkCfgRegs ./MPM_CPU1.obj
    Cmpss1Regs ./MPM_CPU1.obj
    Cmpss2Regs ./MPM_CPU1.obj
    Cmpss3Regs ./MPM_CPU1.obj
    Cmpss5Regs ./MPM_CPU1.obj
    Cmpss6Regs ./MPM_CPU1.obj
    CpuSysRegs ./MPM_CPU1.obj
    CpuTimer0Regs ./MPM_CPU1.obj
    DacaRegs ./MPM_CPU1.obj
    DacbRegs ./MPM_CPU1.obj
    DaccRegs ./MPM_CPU1.obj
    DmaClaSrcSelRegs ./MPM_CPU1.obj
    EPwm1Regs ./MPM_CPU1.obj
    EPwm4Regs ./MPM_CPU1.obj
    EPwmXbarRegs ./MPM_CPU1.obj
    F28x_usDelay ./MPM_CPU1.obj
    GpioCtrlRegs ./MPM_CPU1.obj
    GpioDataRegs ./MPM_CPU1.obj
    InitEPwm1Gpio ./MPM_CPU1.obj
    InitEPwm4Gpio ./MPM_CPU1.obj
    InitGpio ./MPM_CPU1.obj
    InitInputXbar ./MPM_CPU1.obj
    InitPieCtrl ./MPM_CPU1.obj
    InitPieVectTable ./MPM_CPU1.obj
    InitSysCtrl ./MPM_CPU1.obj
    IpcRegs ./MPM_CPU1.obj
    MemCfgRegs ./MPM_CPU1.obj
    PieCtrlRegs ./MPM_CPU1.obj
    PieVectTable ./MPM_CPU1.obj
    SFO ./MPM_CPU1.obj
    main C:\ti\ccs1020\ccs\tools\compiler\ti-cgt-c2000_20.2.2.LTS\lib\rts2800_fpu32_eabi.lib<args_main.c.obj>

    error #10234-D: unresolved symbols remain
    error #10010: errors encountered during linking; "HV_MPM_CPU1.out" not built

    >> Compilation failure
    makefile:153: recipe for target 'HV_MPM_CPU1.out' failed
    gmake[1]: *** [HV_MPM_CPU1.out] Error 1
    makefile:149: recipe for target 'all' failed
    gmake: *** [all] Error 2

    **** Build Finished ****

    Even though the warnings have gone. Have I made a mistake in the linker file? I was unsure where to place the sections, so I just placed them in a section of unused RAM and hoped it would work. 

    Can anyone provide guidance on what is happening, and why?

    Best,
    joel

  • +1 in reply to Joel Holland
    TI__Mastermind 32695 points

    Hi Joel,

    Please make sure you have added the files F2837xD_GlobalVariableDefs.c and F2837xD_Headers_nonBIOS_cpu1.cmd in the CCS build.

    The .c file contains the register struct definitions and the cmd file contains the section mapping.

    Also, note that the F2837x Bitfield contents are still in COFF format. We are planning to move the common files to support EABI as well in upcoming C2000ware release. Meanwhile please refer to the page https://software-dl.ti.com/ccs/esd/documents/C2000_c28x_migration_from_coff_to_eabi.html on the migrating the code from COFF to EABI.

    Please note that the some of the section names such as bss, const etc are different between EABI and COFF formats.

    Regards,

    Veena