TMS320F28337S trapezoidal control using PWMB OUTPUT

Hi user,

Did you configure the dead band generators for mode 2 or 4? Some EPWM module types 0/1 could not bypass dead band PWMB direct to GPIO pins. Perhaps configure overlapping active high output A to make B via dead band configurations for symmetric trapezoidal DSP. Perhaps add GPIO pin configuration for EPWM1 output A/B not show in your code. 

user4565873 said:

i managed to get only PWM on th A output (the TOPs), only high levels on the B outputs (the Bottom)

It's correct, and it's ok for trapezoidal control of the BLDC.

user4565873 said:

But s far i have only a high on output B and no PWM... 

Where should i look

1.  You need to configure the related GPIOs to PWM.

2. Disable the dead band of the ePWM module.

user4565873 said:

i managed to get only PWM on th A output (the TOPs), only high levels on the B outputs (the Bottom)

It's correct, and it's ok for trapezoidal control of the BLDC.

user4565873 :

YEs but not what we want to perform.. So let s say Sensored 120° control… 120° square-wave alternatively leading PWM 

user4565873 said:

But s far i have only a high on output B and no PWM... 

Where should i look

1.  You need to configure the related GPIOs to PWM.

user4565873  DONE, FOc control already tested OK.

2. Disable the dead band of the ePWM module.

user4565873 DONE, this allowed me to get where i am now… but no PWM on output B.

Could you please explain:

"Some EPWM module types 0/1 could not bypass dead band PWMB direct to GPIO pins. Perhaps configure overlapping active high output A to make B via dead band configurations for symmetric trapezoidal DSP."

Dead band is disabled, i figured out it could cause problems before i asked for support

Thank you for insuring my choice.

Any other idea?

thank you! :)

user4565873 said:

Dead band is disabled, i figured out it could cause problems before i asked for support

Perhaps that would be a bit dangerous if you intend on driving 1/2 bridges?

You have to check TRM for your MCU type has EPWM-A tied to B using dead band only. Limitation of type 0/1 modules, type 4 EPWM-B can bypass dead band completely when properly configured. Some ARM based PWM modules have pass through ability too. Can pass CMPB to GPIO pin when dead band is disabled, AKA pass through mode 1.

Can you explain please what do you mean by

Genatco said:

Can pass CMPB to GPIO pin when dead band is disabled, AKA pass through mode 1.

Dead band is disabled when its mode is 0.

Thank you,

PA.

Remark:

Genatco said:

Perhaps that would be a bit dangerous if you intend on driving 1/2 bridges?

Yes, that will be the next point to study… or a cause to not use this command..  but first want to realize what i m asked by my electronics engineers.

user4565873 said:

Dead band is disabled when its mode is 0.

That's the point EPWM-B is not getting out GPIO pin. DB mode 0 does not to pass EPWM-B even after GPIO was configured?

Type 4 EPWM module dead band generators, omits mode 0. Check your MCU technical resource manual (TRM) to see how to configure pass through mode 1 or use A to make B somehow. Type 4 adds DB mode 1 and also allows CMPB via DB out to EPWM-xBar GPIO. The DB config gets a little tricky for slow current decay in 6 step trapezoidal.  

Thank you very much for the detailled explanation! 

Not that i can say it s super clear now.. (because of the various regiqsters) but thanks a lot for the explanation…

Didnt expect to run into such a complex issue when trying a 120° on the newest DSP.

 I have another trail i m Following at the moment.. The AQCTL A settings make my PWM A  disappear.

This make my PWMA disppear.. also:

// CBD
    DrvPWM_EPwm1Regs.AQCTLB.bit.CBD =
    DrvPWM_EPwm2Regs.AQCTLB.bit.CBD =
    DrvPWM_EPwm3Regs.AQCTLB.bit.CBD = AQ_CLEAR;
    // CBU
    DrvPWM_EPwm1Regs.AQCTLB.bit.CBU =
    DrvPWM_EPwm2Regs.AQCTLB.bit.CBU =
    DrvPWM_EPwm3Regs.AQCTLB.bit.CBU = AQ_SET;

    // CAD
    DrvPWM_EPwm1Regs.AQCTLB.bit.CAD =
    DrvPWM_EPwm2Regs.AQCTLB.bit.CAD =
    DrvPWM_EPwm3Regs.AQCTLB.bit.CAD = AQ_NO_ACTION;
    // CAU
    DrvPWM_EPwm1Regs.AQCTLB.bit.CAU =
    DrvPWM_EPwm2Regs.AQCTLB.bit.CAU =
    DrvPWM_EPwm3Regs.AQCTLB.bit.CAU = AQ_NO_ACTION;

    // PRD
    DrvPWM_EPwm1Regs.AQCTLB.bit.PRD =
    DrvPWM_EPwm2Regs.AQCTLB.bit.PRD =
    DrvPWM_EPwm3Regs.AQCTLB.bit.PRD = AQ_NO_ACTION;
    // ZRO
    DrvPWM_EPwm1Regs.AQCTLB.bit.ZRO =
    DrvPWM_EPwm2Regs.AQCTLB.bit.ZRO =
    DrvPWM_EPwm3Regs.AQCTLB.bit.ZRO = AQ_NO_ACTION;

Though it is exactly the configuration given by TI in its exemple:

 DrvPWM_EPwm2Regs.AQCSFRC.bit.CSFA = 0;               /* Forcing disabled on output A of EPWM2            */
              DrvPWM_EPwm2Regs.AQCTLA.bit.CAU = 2;                 /* Set high when CTR = CMPA on UP-count             */
              DrvPWM_EPwm2Regs.AQCTLA.bit.ZRO = 1;                 /* Set low when CTR = Zero                          */
              DrvPWM_EPwm2Regs.CMPA.all = p_u16PWM;                 /* PWM signal on output A of EPWM2 (Q15 -> Q0)      */
              DrvPWM_EPwm2Regs.AQCSFRC.bit.CSFB = 1;               /* Forcing a continuous Low on output A of EPWM2   */

 With this configuration the PWMA operates:

// CBD
    DrvPWM_EPwm1Regs.AQCTLB.bit.CBD =
    DrvPWM_EPwm2Regs.AQCTLB.bit.CBD =
    DrvPWM_EPwm3Regs.AQCTLB.bit.CBD = AQ_SET;
    // CBU
    DrvPWM_EPwm1Regs.AQCTLB.bit.CBU =
    DrvPWM_EPwm2Regs.AQCTLB.bit.CBU =
    DrvPWM_EPwm3Regs.AQCTLB.bit.CBU = AQ_SET;

    // CAD
    DrvPWM_EPwm1Regs.AQCTLB.bit.CAD =
    DrvPWM_EPwm2Regs.AQCTLB.bit.CAD =
    DrvPWM_EPwm3Regs.AQCTLB.bit.CAD = AQ_NO_ACTION;
    // CAU
    DrvPWM_EPwm1Regs.AQCTLB.bit.CAU =
    DrvPWM_EPwm2Regs.AQCTLB.bit.CAU =
    DrvPWM_EPwm3Regs.AQCTLB.bit.CAU = AQ_NO_ACTION;

    // PRD
    DrvPWM_EPwm1Regs.AQCTLB.bit.PRD =
    DrvPWM_EPwm2Regs.AQCTLB.bit.PRD =
    DrvPWM_EPwm3Regs.AQCTLB.bit.PRD = AQ_NO_ACTION;
    // ZRO
    DrvPWM_EPwm1Regs.AQCTLB.bit.ZRO =
    DrvPWM_EPwm2Regs.AQCTLB.bit.ZRO =
    DrvPWM_EPwm3Regs.AQCTLB.bit.ZRO = AQ_NO_ACTION;

 Do you see any relation in this configuration and my PWM-B output issue?

Thank you,

PA.

As you can see the dead band generators sit on the outside of the EPWM-CMPA/B outputs. And the register reset binary defaults may not produce the results your expecting .

Please use C2000ware driverlib functions to configure peripheral registers . The datasheet, TRM technical peripheral discussions relate more to your questions, will aid you greatly. The above coding style is not giving enough detail of what is actually being touched under the hood.

 Here s the code for PWM configurations:

I just have a problem wiht sequencing PWMs on120°.

/*
     * Below registers are "protected", allow access.
     */
    EALLOW;
    // Enable EPWMs module CLOCK
    CpuSysRegs.PCLKCR2.bit.EPWM1 = 1; // ePWM1
    CpuSysRegs.PCLKCR2.bit.EPWM2 = 1; // ePWM2
    CpuSysRegs.PCLKCR2.bit.EPWM3 = 1; // ePWM3

    CpuSysRegs.PCLKCR0.bit.TBCLKSYNC = 0; // Stop all the TB clocks

    // Disable register access
    EDIS;

    /*******************/
    /* TBCTL registers */
    /*******************/
    // Count up after sync. event
    DrvPWM_EPwm1Regs.TBCTL.bit.PHSDIR =
    DrvPWM_EPwm2Regs.TBCTL.bit.PHSDIR =
    DrvPWM_EPwm3Regs.TBCTL.bit.PHSDIR = TB_UP;
    // TBCLK = SYSCLKOUT / (HSPCLKDIV * CLKDIV)
    // CLKDIV = 1
    DrvPWM_EPwm1Regs.TBCTL.bit.CLKDIV =
    DrvPWM_EPwm2Regs.TBCTL.bit.CLKDIV =
    DrvPWM_EPwm3Regs.TBCTL.bit.CLKDIV = TB_DIV1;
    // HSPCLKDIV = 1
    DrvPWM_EPwm1Regs.TBCTL.bit.HSPCLKDIV =
    DrvPWM_EPwm2Regs.TBCTL.bit.HSPCLKDIV =
    DrvPWM_EPwm3Regs.TBCTL.bit.HSPCLKDIV = TB_DIV1;
    // SYNCOSEL: Setup Sync => Pass through
    DrvPWM_EPwm1Regs.TBCTL.bit.SYNCOSEL =
    DrvPWM_EPwm2Regs.TBCTL.bit.SYNCOSEL =
    DrvPWM_EPwm3Regs.TBCTL.bit.SYNCOSEL = TB_SYNC_IN;
    // PRDLD: TBPRD register loading
    DrvPWM_EPwm1Regs.TBCTL.bit.PRDLD =
    DrvPWM_EPwm2Regs.TBCTL.bit.PRDLD =
    DrvPWM_EPwm3Regs.TBCTL.bit.PRDLD = TB_SHADOW;
    // PHSEN: Allow each timer to be sync'ed
    DrvPWM_EPwm1Regs.TBCTL.bit.PHSEN =
    DrvPWM_EPwm2Regs.TBCTL.bit.PHSEN =
    DrvPWM_EPwm3Regs.TBCTL.bit.PHSEN = TB_DISABLE;
    // CTRMODE: Up-down-count mode
    DrvPWM_EPwm1Regs.TBCTL.bit.CTRMODE =
    DrvPWM_EPwm2Regs.TBCTL.bit.CTRMODE =
    DrvPWM_EPwm3Regs.TBCTL.bit.CTRMODE = TB_COUNT_UPDOWN;

    /********************/
    /* CMPCTL registers */
    /********************/
    // SHDWAMODE
    DrvPWM_EPwm1Regs.CMPCTL.bit.SHDWAMODE =
    DrvPWM_EPwm2Regs.CMPCTL.bit.SHDWAMODE =
    DrvPWM_EPwm3Regs.CMPCTL.bit.SHDWAMODE = CC_SHADOW;
    // SHDWBMODE
    DrvPWM_EPwm1Regs.CMPCTL.bit.SHDWBMODE =
    DrvPWM_EPwm2Regs.CMPCTL.bit.SHDWBMODE =
    DrvPWM_EPwm3Regs.CMPCTL.bit.SHDWBMODE = CC_SHADOW;
    // LOADAMODE
    DrvPWM_EPwm1Regs.CMPCTL.bit.LOADAMODE =
    DrvPWM_EPwm2Regs.CMPCTL.bit.LOADAMODE =
    DrvPWM_EPwm3Regs.CMPCTL.bit.LOADAMODE = CC_CTR_ZERO;
    // LOADAMODE
    DrvPWM_EPwm1Regs.CMPCTL.bit.LOADBMODE =
    DrvPWM_EPwm2Regs.CMPCTL.bit.LOADBMODE =
    DrvPWM_EPwm3Regs.CMPCTL.bit.LOADBMODE = CC_CTR_ZERO;

    /*******************/
    /* TBPHS registers */
    /*******************/
    DrvPWM_EPwm1Regs.TBPHS.bit.TBPHS =
    DrvPWM_EPwm2Regs.TBPHS.bit.TBPHS =
    DrvPWM_EPwm3Regs.TBPHS.bit.TBPHS = 0x0000;

    /*******************/
    /* TBPRD registers */
    /*******************/
    DrvPWM_EPwm1Regs.TBPRD = DrvPWM_epwm.epwm1timertbprd;
    DrvPWM_EPwm2Regs.TBPRD = DrvPWM_epwm.epwm2timertbprd;
    DrvPWM_EPwm3Regs.TBPRD = DrvPWM_epwm.epwm3timertbprd;

    /******************/
    /* CMPA registers */
    /******************/
    DrvPWM_EPwm1Regs.CMPA.bit.CMPA = DrvPWM_epwm.epwm1cmpa;
    DrvPWM_EPwm2Regs.CMPA.bit.CMPA = DrvPWM_epwm.epwm2cmpa;
    DrvPWM_EPwm3Regs.CMPA.bit.CMPA = DrvPWM_epwm.epwm3cmpa;

    /******************/
    /* CMPB registers */
    /******************/
    DrvPWM_EPwm1Regs.CMPB.bit.CMPB = DrvPWM_epwm.epwm1cmpb;
    DrvPWM_EPwm2Regs.CMPB.bit.CMPB = DrvPWM_epwm.epwm2cmpb;
    DrvPWM_EPwm3Regs.CMPB.bit.CMPB = DrvPWM_epwm.epwm3cmpb;

    /********************/
    /* AQCTLA registers */
    /********************/
    // CBD
    DrvPWM_EPwm1Regs.AQCTLA.bit.CBD =
    DrvPWM_EPwm2Regs.AQCTLA.bit.CBD =
    DrvPWM_EPwm3Regs.AQCTLA.bit.CBD = AQ_NO_ACTION;
    // CBD
    DrvPWM_EPwm1Regs.AQCTLA.bit.CBU =
    DrvPWM_EPwm2Regs.AQCTLA.bit.CBU =
    DrvPWM_EPwm3Regs.AQCTLA.bit.CBU = AQ_NO_ACTION;
    // CAD
    DrvPWM_EPwm1Regs.AQCTLA.bit.CAD =
    DrvPWM_EPwm2Regs.AQCTLA.bit.CAD =
    DrvPWM_EPwm3Regs.AQCTLA.bit.CAD = AQ_CLEAR;
    // CAU
    DrvPWM_EPwm1Regs.AQCTLA.bit.CAU =
    DrvPWM_EPwm2Regs.AQCTLA.bit.CAU =
    DrvPWM_EPwm3Regs.AQCTLA.bit.CAU = AQ_SET;
    // PRD
    DrvPWM_EPwm1Regs.AQCTLA.bit.PRD =
    DrvPWM_EPwm2Regs.AQCTLA.bit.PRD =
    DrvPWM_EPwm3Regs.AQCTLA.bit.PRD = AQ_NO_ACTION;
    // ZRO
    DrvPWM_EPwm1Regs.AQCTLA.bit.ZRO =
    DrvPWM_EPwm2Regs.AQCTLA.bit.ZRO =
    DrvPWM_EPwm3Regs.AQCTLA.bit.ZRO = AQ_NO_ACTION;

    /********************/
    /* AQCTLB registers */
    /********************/
    // CBD
    DrvPWM_EPwm1Regs.AQCTLB.bit.CBD =
    DrvPWM_EPwm2Regs.AQCTLB.bit.CBD =
    DrvPWM_EPwm3Regs.AQCTLB.bit.CBD = AQ_NO_ACTION;
    // CBD
    DrvPWM_EPwm1Regs.AQCTLB.bit.CBU =
    DrvPWM_EPwm2Regs.AQCTLB.bit.CBU =
    DrvPWM_EPwm3Regs.AQCTLB.bit.CBU = AQ_NO_ACTION;

    // CAD
    DrvPWM_EPwm1Regs.AQCTLB.bit.CAD =
    DrvPWM_EPwm2Regs.AQCTLB.bit.CAD =
    DrvPWM_EPwm3Regs.AQCTLB.bit.CAD = AQ_CLEAR;
    // CAU
    DrvPWM_EPwm1Regs.AQCTLB.bit.CAU =
    DrvPWM_EPwm2Regs.AQCTLB.bit.CAU =
    DrvPWM_EPwm3Regs.AQCTLB.bit.CAU = AQ_SET;

    // PRD
    DrvPWM_EPwm1Regs.AQCTLB.bit.PRD =
    DrvPWM_EPwm2Regs.AQCTLB.bit.PRD =
    DrvPWM_EPwm3Regs.AQCTLB.bit.PRD = AQ_NO_ACTION;
    // ZRO
    DrvPWM_EPwm1Regs.AQCTLB.bit.ZRO =
    DrvPWM_EPwm2Regs.AQCTLB.bit.ZRO =
    DrvPWM_EPwm3Regs.AQCTLB.bit.ZRO = AQ_NO_ACTION;

    /*********************/
    /* AQCSFRC registers */
    /*********************/
    // Force Output A to low state
    DrvPWM_EPwm1Regs.AQCSFRC.bit.CSFA =
    DrvPWM_EPwm2Regs.AQCSFRC.bit.CSFA =
    DrvPWM_EPwm3Regs.AQCSFRC.bit.CSFA = 0x1;

    // Force Output B to low state
 DrvPWM_EPwm1Regs.AQCSFRC.bit.CSFB =
 DrvPWM_EPwm2Regs.AQCSFRC.bit.CSFB =
 DrvPWM_EPwm3Regs.AQCSFRC.bit.CSFB = 0x1;

     /*******************/
    /* DBCTL registers */
    /*******************/
    DrvPWM_EPwm1Regs.DBCTL.all = 0x0;
    DrvPWM_EPwm2Regs.DBCTL.all = 0x0;
    DrvPWM_EPwm3Regs.DBCTL.all = 0x0;
 
    DrvPWM_EPwm1Regs.DBCTL.bit.OUT_MODE =
    DrvPWM_EPwm2Regs.DBCTL.bit.OUT_MODE =
    DrvPWM_EPwm3Regs.DBCTL.bit.OUT_MODE = DB_DISABLE;
    /*
     * Disable register access
     */
    EDIS;

    // Finally configure GPIOs for PWM
    x_vDrvGPIO_CoreConfigurePWM();
    //and EVASOC
    x_vDrvGPIO_CoreConfigureEVSOC();

 /*
  * Brief: epwm parameters initialization
  */

    /* below registers are "protected", allow access.*/
  EALLOW;

  CpuSysRegs.PCLKCR0.bit.TBCLKSYNC = 1; // Start all the timers synced

 /* Interrupt for control loop */
   DrvPWM_EPwm1Regs.ETSEL.bit.INTSEL = ET_CTR_PRD;     // Select INT on reload.
   DrvPWM_EPwm1Regs.ETSEL.bit.INTEN = 1;                // Enable INT
   DrvPWM_EPwm1Regs.ETPS.bit.INTPRD = ET_1ST;           // Generate INT on 1st event

      //enable SOCA
      //DrvPWM_EPwm1Regs.TBCTL.bit.CTRMODE = 0; //unfreeze, and enter up count mode
      DrvPWM_EPwm1Regs.ETSEL.bit.SOCAEN = 1;
      DrvPWM_EPwm1Regs.ETSEL.bit.SOCASEL = ET_CTR_PRD; // Start IT @ counter = period.

   /*
    *  Disable register access
    */
      EDIS;

}

The sequence based on the hall sensor position:

The examples provided by TI is a Up counter.. I want to use up_down.

switch (p_u16HallSensorSeq)

{

case 1:

{

DrvPWM_EPwm1Regs.AQCSFRC.bit.CSFB = 0; /* Forcing disabled on output B of EPWM1 */

DrvPWM_EPwm1Regs.AQCTLB.bit.CBU = 2; /* Set high when CTR = CMPB on UP-count */

DrvPWM_EPwm1Regs.AQCTLB.bit.CBD = 1; /* Set low when CTR = CMPB on DOWN-count */ HERE TI does BIT.ZERO =1

DrvPWM_EPwm1Regs.CMPB.all = p_u16PWM; /* PWM signal on output B of EPWM1 */

DrvPWM_EPwm1Regs.AQCSFRC.bit.CSFA = 1; /* Forcing a continuous LOw on output A of EPWM1 */

/* */

DrvPWM_EPwm2Regs.AQCSFRC.bit.CSFA = 2; /* Forcing a continuous High on output A of EPWM2 */

DrvPWM_EPwm2Regs.AQCSFRC.bit.CSFB = 1; /* Forcing a continuous Low on output B of EPWM2 */

/* */

DrvPWM_EPwm3Regs.AQCSFRC.bit.CSFA = 1; /* Forcing a continuous Low on output A of EPWM3 */

DrvPWM_EPwm3Regs.AQCSFRC.bit.CSFB = 1; /* Forcing a continuous Low on output B of EPWM3 */

}

break;

case 5:

{

DrvPWM_EPwm1Regs.AQCSFRC.bit.CSFA = 1; /* Forcing a continuous Low on output A of EPWM1 */

DrvPWM_EPwm1Regs.AQCSFRC.bit.CSFB = 2; /* Forcing a continuous High on output B of EPWM1 */

DrvPWM_EPwm2Regs.AQCSFRC.bit.CSFA = 1; /* Forcing a continuous Low on output A of EPWM2 */

DrvPWM_EPwm2Regs.AQCSFRC.bit.CSFB = 1; /* Forcing a continuous Low on output B of EPWM2 */

DrvPWM_EPwm3Regs.AQCSFRC.bit.CSFA = 0; /* Forcing disabled on output A of EPWM3 */

DrvPWM_EPwm3Regs.AQCTLA.bit.CAU = 2; /* Set high when CTR = CMPA on UP-count */

DrvPWM_EPwm3Regs.AQCTLA.bit.CAD = 1; /* Set low when CTR = CMPA on DOWN-count */HERE TI does BIT.ZERO =1

#endif

DrvPWM_EPwm3Regs.CMPA.all = p_u16PWM; /* PWM signal on output A of EPWM3 */

DrvPWM_EPwm3Regs.AQCSFRC.bit.CSFB = 1; /* Forcing a continuous Low on output B of EPWM3 */

}

break;

case 4:

{

DrvPWM_EPwm1Regs.AQCSFRC.bit.CSFA = 1; /* Forcing a continuous Low on output A of EPWM1 */

DrvPWM_EPwm1Regs.AQCSFRC.bit.CSFB = 1; /* Forcing a continuous Low on output B of EPWM1 */

DrvPWM_EPwm2Regs.AQCSFRC.bit.CSFB = 0; /* Forcing disabled on output B of EPWM2 */

DrvPWM_EPwm2Regs.AQCTLB.bit.CBU = 2; /* Set high when CTR = CMPB on UP-count */

DrvPWM_EPwm2Regs.AQCTLB.bit.CBD = 1; /* Set low when CTR = CMPB on DOWN-count */HERE TI does BIT.ZERO =1

DrvPWM_EPwm2Regs.CMPB.all = p_u16PWM; /* PWM signal on output B of EPWM2 (Q15 -> Q0) */

DrvPWM_EPwm2Regs.AQCSFRC.bit.CSFA = 1; /* Forcing a continuous Low on output A of EPWM2 */

/* */

DrvPWM_EPwm3Regs.AQCSFRC.bit.CSFA = 2; /* Forcing a continuous High on output A of EPWM3 */

DrvPWM_EPwm3Regs.AQCSFRC.bit.CSFB = 1; /* Forcing a continuous Low on output B of EPWM3 */

}

break;

case 6:

{

DrvPWM_EPwm1Regs.AQCSFRC.bit.CSFA = 0; /* Forcing disabledd on output A of EPWM1 */

DrvPWM_EPwm1Regs.AQCTLA.bit.CAU = 2; /* Set high when CTR = CMPA on UP-count */

DrvPWM_EPwm1Regs.AQCTLA.bit.CAD = 1; /* Set low when CTR = CMPA on Down-count */HERE TI does BIT.ZERO =1

DrvPWM_EPwm1Regs.CMPA.all = p_u16PWM; /* PWM signal on output A of EPWM1 */

DrvPWM_EPwm1Regs.AQCSFRC.bit.CSFB = 1; /* Forcing a continuous Low on output B of EPWM1 */

/* */

DrvPWM_EPwm2Regs.AQCSFRC.bit.CSFA = 1; /* Forcing a continuous Low on output A of EPWM2 */

DrvPWM_EPwm2Regs.AQCSFRC.bit.CSFB = 2; /* Forcing a continuous High on output B of EPWM2 */

/* */

DrvPWM_EPwm3Regs.AQCSFRC.bit.CSFA = 1; /* Forcing a continuous Low on output A of EPWM3 */

DrvPWM_EPwm3Regs.AQCSFRC.bit.CSFB = 1; /* Forcing a continuous Low on output B of EPWM3 */

} /* */

break;

case 2:

{

DrvPWM_EPwm1Regs.AQCSFRC.bit.CSFA = 2; /* Forcing a continuous HIgh on output A of EPWM1 */

DrvPWM_EPwm1Regs.AQCSFRC.bit.CSFB = 1; /* Forcing a continuous Low on output B of EPwm1 */

/* */

DrvPWM_EPwm2Regs.AQCSFRC.bit.CSFA = 1; /* Forcing a continuous Low on output A of EPWM2 */

DrvPWM_EPwm2Regs.AQCSFRC.bit.CSFB = 1; /* Forcing a continuous Low on output B of EPWM2 */

/* */

DrvPWM_EPwm3Regs.AQCSFRC.bit.CSFB = 0; /* Forcing disabled on output B of EPWM3 */

DrvPWM_EPwm3Regs.AQCTLB.bit.CBU = 2; /* Set high when CTR = CMPB on UP-count */

DrvPWM_EPwm3Regs.AQCTLB.bit.CBD = 1; /* Set low when CTR = CMPB on Down-count */HERE TI does BIT.ZERO =1

DrvPWM_EPwm3Regs.CMPB.all = p_u16PWM; /* PWM signal on output B of EPWM3 */

DrvPWM_EPwm3Regs.AQCSFRC.bit.CSFA = 1; /* Forcing a continuous Low on output A of EPWM3 */

}

break;

case 3:

{

DrvPWM_EPwm1Regs.AQCSFRC.bit.CSFA = 1; /* Forcing a continuous Low on output A of EPWM1 */

DrvPWM_EPwm1Regs.AQCSFRC.bit.CSFB = 1; /* Forcing a continuous Low on output B of EPWM1 */

/* */

DrvPWM_EPwm2Regs.AQCSFRC.bit.CSFA = 0; /* Forcing disabled on output A of EPWM2 */

DrvPWM_EPwm2Regs.AQCTLA.bit.CAU = 2; /* Set high when CTR = CMPA on UP-count */

DrvPWM_EPwm2Regs.AQCTLA.bit.CAD = 1; /* Set low when CTR = CMPA on Down-count */

DrvPWM_EPwm2Regs.CMPA.all = p_u16PWM; /* PWM signal on output A of EPWM2 (Q15 -> Q0) */

DrvPWM_EPwm2Regs.AQCSFRC.bit.CSFB = 1; /* Forcing a continuous Low on output A of EPWM2 */

/* */

DrvPWM_EPwm3Regs.AQCSFRC.bit.CSFA = 1; /* Forcing a continuous Low on output A of EPWM3 */

DrvPWM_EPwm3Regs.AQCSFRC.bit.CSFB = 2; /* Forcing a continuous High on output B of EPWM3 */

}

break;

}

The GPIO init identical for PWM1,2 and here 3:

(based on TI code, of course)

On my point of view GPIO are working fine...

EALLOW;

/* Disable internal pull-up for the selected output pins

for reduced power consumption */

// Pull-ups can be enabled or disabled by the user.

// This will enable the pullups for the specified pins.

GpioCtrlRegs.GPAPUD.bit.GPIO4 = 1; // Disable pull-up on GPIO4 (EPWM3A)

GpioCtrlRegs.GPAPUD.bit.GPIO5 = 1; // Disable pull-up on GPIO5 (EPWM3B)

/* Configure EPwm-3 pins using GPIO regs*/

// This specifies which of the possible GPIO pins will be EPWM3 functional pins.

// Comment out other unwanted lines.

GpioCtrlRegs.GPAMUX1.bit.GPIO4 = 1; // Configure GPIO4 as EPWM3A

GpioCtrlRegs.GPAMUX1.bit.GPIO5 = 1; // Configure GPIO5 as EPWM3B

EDIS;

user4565873 said:

The examples provided by TI is a Up counter.. I want to use up_down.

You need to configure TBPRD control register for Up/Down count mode.  

user4565873 said:

    DrvPWM_EPwm1Regs.DBCTL.bit.OUT_MODE =
    DrvPWM_EPwm2Regs.DBCTL.bit.OUT_MODE =
    DrvPWM_EPwm3Regs.DBCTL.bit.OUT_MODE = DB_DISABLE;

Why only disabled last EPWM? Note may disable all 3 to bypass DB completely, disabled mode 0 might be reset default anyway. 

user4565873 said:

case 1:

{

DrvPWM_EPwm1Regs.AQCSFRC.bit.CSFB = 0; /* Forcing disabled on output B of EPWM1 */

DrvPWM_EPwm1Regs.AQCTLB.bit.CBU = 2; /* Set high when CTR = CMPB on UP-count */

DrvPWM_EPwm1Regs.AQCTLB.bit.CBD = 1; /* Set low when CTR = CMPB on DOWN-count */ HERE TI does BIT.ZERO =1

DrvPWM_EPwm1Regs.CMPB.all = p_u16PWM; /* PWM signal on output B of EPWM1 */

DrvPWM_EPwm1Regs.AQCSFRC.bit.CSFA = 1; /* Forcing a continuous LOw on output A of EPWM1 */

Look like you comment all actions EPWM not need to do, select 1 action only for each case.

Make sure the EPWM clocks are enabled.

SysCtl_enablePeripheral(SYSCTL_PERIPH_CLK_EPWM1);
SysCtl_enablePeripheral(SYSCTL_PERIPH_CLK_EPWM2);
SysCtl_enablePeripheral(SYSCTL_PERIPH_CLK_EPWM3); 

user4565873 said:

The GPIO init identical for PWM1,2 and here 3:

What about the GPIO direction mode control register?

Thanks for the help, but nothing so far.

GPiO and clocks are not the pb.. I can get full high or full low on PWMB just the chopping is not performed. I can perfectly perform a FOC control of the motor.

Just when i try to perform symetrical 120° with alternative chopping on PWM A and B.. i dont get chopping on ouptut B and i get only assymetrical chopping on PWMA. 

Genatco said:

Look like you comment all actions EPWM not need to do, select 1 action only for each case.

This is code extracted from TI C2000 ware, i think it s supposed to work.. ;)

user4565873 said:

GPiO and clocks are not the pb.. I can get full high or full low on PWMB just the chopping is not performed. I can perfectly perform a FOC control of the motor.

Details you never mention until now do not serve well to find solutions. DB control registers were not configured EPWM1 or EPWM2 above code. Running HALL FOC with no dead band enabled can easily lead to shoot through .

Please use CCS debug to view EPWM registers and ensure the configuration is proper for your needs.