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TMS320F280049: PMBus CLK_HIGH_DETECTED bit won't get set

Part Number: TMS320F280049


Dear C2000 expert,

When I testing some of abnormal situation for pmbus slave mode, I found that the CLK_HIGH_DETECTED in PMBSTS won't get set. Can you please help me know why?

My testing condition is that master read block data from slaver, and I made master hold the clock high after reading one byte (not finish reading all bytes). This is abnormal condition for master. But in this condition, I found that CLK_HIGH_DETECTED in PMBSTS won't get set. Please see below picture that capture PMBSTS value via CCS. 

Please see my testing waveform as below, the first waveform show that the master hold the clock to high but not finished all reading bytes, slave pull down data line to low. The second waveform shows the last byte that master read from slaver before enter into abnormal situation.

Our customer systems require that the slaver have to recover to normal state(clk and data release to idle) once detecting any of abnormal situation happens including master. Can you share some suggestion in this case? Thanks...

My initialized code for PMBus:

pmbus_base = PMBUSA_BASE;
pmbus_slave_addr = 0x58u;

PMBus_initSlaveMode(pmbus_base,pmbus_slave_addr,0x7fu);
PMBus_configSlave(pmbus_base,PMBUS_PMBSC_PEC_ENA|PMBUS_PMBSC_RX_BYTE_ACK_CNT_M);

/* Configure the PMBUS module clock to be PMBUS_MODULE_FREQ_MAX */
uint32_t moduleFreq = PMBus_configModuleClock(PMBUSA_BASE, (PMBUS_MODULE_FREQ_MAX>>1), PMBUS_SYS_FREQ_MAX);

/* Configure the PMBUS bus clock */
PMBus_configBusClock(PMBUSA_BASE, PMBUS_CLOCKMODE_STANDARD, moduleFreq);

Regards,

Jack

  • Jack,

    Do you see this problem in both master and slave configuration? Can you please provide full PMBus configuration code?

    Also, do you see CLK_LOW_TIMEOUT being set properly?

    Regards,

    Manoj

  • Manoj,

    I just use F280049 as pmbus slaver, and didn't configure as master for testing purpose yet. Sorry, I was not allowed to share the full pmbus code with you.

    But I think this can be reproduced with using TI's pmbus stack code as well. In read block sequence, master hold the clock to high after one byte read from slaver.

    CLK_LOW_TIMEOUT can be set properly in my testing, and it works well.

    Regards,

    Jack

  • Jack,

    I need some time to debug this issue. Let me try re-creating the failure from myside and get back with you.

    Please expect upto 2 - 3 business day for a response.

    Regards,

    Manoj

  • Manoj,

    Thanks for supporting here. It's OK.

    Regards,

    Jack

  • Jack,

    Design team confirmed that they were able to get CLK_HIGH_DETECTED bit set without any problem. They are asking for programming sequence of PMBus. Its okay even if you share pseudo code.

    Regards,

    Manoj

  • Manoj,

    Do you have custimized pmbus/i2c master which could insert any of fault during message transmition? If no custimized master, this issue will be hard to reproduce.

    Regards,

    Jack

  • Jack,

    We use two devices talk to each other using PMBus to reproduce the issue.

    Regards,

    Manoj

  • Jack,

    CLK_HIGH_DETECTED bit should be used by PMBus master and not PMBus slave. According to PMBus specs, CLK_HIGH_DETECTED bit provides a guaranteed method for masters to detect bus idle condition.

    I want to understand how PMBus CLK_HIGH_DETECTED bit affects your slave operation.

    Regards,

    Manoj

  • Manoj,

    Please see my testing waveform in my first post, here I will reproduce it as below. Before the eom of pmbus read block was inserted, master hold the clock high and do not continue to toggle clock to read rest of bytes, and pmbus slaver will hold the data low. This causes pmbus slaver won't recover properly. I need conditions or flags that knows current pmbus slaver works abnormal, then recover pmbus hardware(maybe reset hardware ) and pmbus state machine.

    But there is no extra bits in pmbus status register could tell me that pmbus hardware works abnormal, can you share some suggestions?

    Regards,

    Jack

  • Jack,

    I will check on this. But, here is my concern. If the PMBus slave resets the module on abnormal condition, how will your PMBus master know that PMBus slave got reset?

    Also, what is your master device PMBus device?

    Regards,

    Manoj

  • Manoj,

    Good point.  This issue actually caulsed by master, the system requires slaver can be recovered properly even master cause transmission abnormal. In this case, the slaver has always pull down data line, it's abnormal. So it's OK to reset pmbus slaver and won't affect master.

    My master is server system.

  • Jack,

    I tried to re-create abnormal condition and also didn't see CLK_HIGH_DETECTED bit get set in PMBus slave mode.

    I have requested design team to confirm whether CLK_HIGH_DETECTED would work only when PMBus is configured as master. If the reply comes affirmative, you might need to implement a workaround along this lines.

    When PMBSTS.UNIT_BUSY bit is set, it indicates that PMBus interface is busy. We can use this feature and a timer to implement a workaround as shown below:-

     If UNIT_BUSY bit stays high with no PMBus transaction then reset the PMBus module.
             – Set up firmware timer in timer interrupt to detect lockup
             – If it times out, reset PMBus peripheral, firmware
             – PMBus firmware clears timer whenever data is transmitted or received on bus (or)

             – when UNIT_BUSY bit is not set (meaning PMBus interface is not busy)
             – Timer interval depends on PMBus host speed

    Regards,

    Manoj

  • Manoj,

    Cool. I see UNIT_BUSY get set under this condition.

    Regards,

    Jack

  • Jack,

    You can go-ahead with this idea. But, it will keep you posted when design confirms that CLK_HIGH_DETECTED works only for PMBus master configuration.

    Have already posted this question to them. It generally takes atleast 1 week for them to answer it. I shall keep you posted.

    Regards,

    Manoj