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LAUNCHXL-F280049C: ADC clock this clock

Genatco
Guru 56398 points

Part Number: LAUNCHXL-F280049C

SPRUI33D – NOVEMBER 2015 – REVISED SEPTEMBER 2020

13.2.1 Clock Configuration
The base ADC clock is provided directly by the system clock (SYSCLK). "This clock is" used to generate the ADC acquisition window. The register ADCCTL2 has a PRESCALE field that determines the ADCCLK. The ADCCLK is used to clock the converter. The core requires approximately 10.5 ADCCLK cycles to process a voltage into a conversion result.

It is necessary for the user to determine the required duration of the acquisition window, see Section 13.13.2.

Given the reference of the ADC clock, "This clock is" to me infers the ADC clock, not the derived from source SYSCLK. The 13.2.1 statement is vague misleading one to believe SYSCLK was the acquisition source clock rate and EOC interrupt pulse source. TRM omitting any kind of peripheral main clock tree or any clock source identification ADC block Fig.13-1 is mind numbing.  Adding clock sources in block figures will remove any such question of who is the real clock source. The words "fore mentioned or latter" would infer SYSCLK generates the acquisition window.

Yet 50Mhz ADC sample acquisition rate is not slow by any means and should produce well over 2.5MSPS, upward 3MSPS. The AD converter clocks at SYSCLK speed in other TI family ADC peripherals so the digital FIFO data timing aligns with CPU system BUS timing. 

  • 0
    TI__Mastermind 43720 points

    Hi GI,

    Thanks for the feedback!  I see the confusion.  Instead of just stating "This clock is" on the next sentence as previous sentence had referred to both ADCLK and SYSCLK, we have to be specific what clock this actually is.  In this case, "This clock is" refers to SYSCLK.  The timing diagrams and tables in section 13.12.1 are all expressed in terms of SYSCLK.  You are correct, SH, EOC and interrupt timings tLAT, tEOC, tINT are all in terms of SYSCLK in the timing diagram.  The conversion result being ready by 10.5 ADCCLKs is factored in on the values tabulated in Table 13-9, hence the different values of tLAT, tEOC, tINT expressed in terms of SYSCLK for the different ADC clock prescaler values.

    And lastly, yes with a 100MHz (10nS) SYSCLK rating for F28004x,  higher ADC throughput can be attained.  This is reflected in the datasheet SPRS945F, where maximum attainable ADC sampling rate is 3.45MSPS (p.1 and Table 7.10.1.2.1).

    Hope this clarifies the confusion.  I have submitted a ticket to have the the statement changed to "SYSCLK is used to generate the ADC acquisition window".  Next version of the TRM should have this wordings.

    Regards,

    Joseph

  • 0 in reply to Joseph Casuga
    Guru 56398 points

    Hi Joseph,

    Joseph Casuga said:
    I have submitted a ticket to have the the statement changed to "SYSCLK is used to generate the ADC acquisition window".

    I read that idea noted in several TRM sections. Yet that does not seem correct in perspective of asynchronous channel sampling. The x49c datasheet   Fig.7-11 is incomplete and leaves out ADC blocks shown in TRM Fig.13-1 leading to assumptions. Are the DC FIFO's on the SYSCLK side or the ADCCLK side of town?

    Seemingly the FIFO data from the converter is clocked onto blue bus Perx.SYSCLK. The analog sampling S/H acquisition frames are ADCCLK related in my opinion, have no direct tie with Perx.SYSCLK. Since the input channel data is analog sample time and not digital at the Nyquist sample rate where the S/H window size relates to ADCCLK prior to the digital conversion.

    Example: 140ns acquisition 10ns Perx.SYSLCK or x14 S/H window seems questionable. Logically the window is 280ns (x14) ADCCLK related, from 50mHz perspective as acquisitions occur via S/H circuit, not the digital converter. The analog data is asynchronous (S/H) until the converter makes it synchronous as Perx.SYSCLK places FIFO data onto the blue bus for CPU accumulator. The TRM author seems to have looked at the S/H  acquisitions from the CPU perspective outward rather than the peripheral perspective inward.

    Good reason why Fig.7-11 or Fig.5-32 needs to have clock inputs shown for the peripheral side.  

  • +1 in reply to Genatco
    TI__Mastermind 43720 points

    Hi GI,

    ADCCLK is responsible for the quantization/conversion.  SYSCLK is used for SH and used to clock the rest of the ADC wrapper functions (FIFO, interrupts, EOC, SOC control, PPB, timestamps..etc).

    ADCCLK/SYSCLK use is stated in several parts of the TRM as well:

    Would it have helped eliminate the confusion on ADCLK/SYSCLK use in ADC if block diagram included the added clock tree (in red)

    Regards,

    Joseph

  • 0 in reply to Joseph Casuga
    Guru 56398 points
    Joseph Casuga said:
    .  SYSCLK is used for SH

    Your figure reveal is not so believable, though I could believe SOC block being Perx.SYSCLK. Yet never for the SH, that is acquisition relative to ADCCLK alone. The red lines; where exactly is ADCCLK doing any clocking of the analog channel data? The converter though is very believable to be Perx.SYSCLK driven as to synchronize analog asynchronous data for the CPU to digest in it's MOSC time domain. 

  • 0 in reply to Genatco
    Guru 56398 points
    Genatco said:
    Yet never for the SH,

    Why would Switch Fig.13.3 hold data at twice the conversion rate? When the RC time constant for acquisition is based on the ADC clock sample rate. Perx.SYSCLK has no part in the SPS rate of the ADC to sample at 3.45MSPS if the SH block is ADCCLK driven. That will reduce the SPS by the amount of pipe line restriction, no gas at these pumps Laughing.

    For example the TM4C1294 ADC via 32mHz ADCCLK is 2MSPS relative to SH bandwidth and reduced sample rate relative to the Rs input impedance.

  • 0 in reply to Genatco
    TI__Mastermind 43720 points

    I think you are assuming that TM4Cxxx ADC is similar to F280049 ADC.  Both are 12-bit ADC but they are entirely different designs.  TM4Cxxx ADC events are all based off of ADCCLK.  F280049 ADC, as described in the TRM operates on SYSCLK and ADCCLK.  ADCCLK is used by the SAR for the quantization.  Rest of the ADC events which include SH, data transfers and interrupts and the other functions done by the ADC wrapper are clocked by SYSCLK.  That is how the F280049 ADC is designed to operate.

  • 0 in reply to Joseph Casuga
    Guru 56398 points
    Joseph Casuga said:
    TM4Cxxx ADC events are all based off of ADCCLK. 

    No TM4C ADC use both, SYSCLK 120mHz for converter circular FIFO's and 32mHz ADC clock for Ca switch sampling 2MSPS, 16mHz for 1MSPS. 

    Thanks for adding the clocks Grinning