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TMS320F28379D: GPIO control from core 2

Part Number: TMS320F28379D
Other Parts Discussed in Thread: C2000WARE

I'm working on converting a project to use both cores on this device, however I'm having issues getting the GPIOs to work from core 2. 

My pin setup is basically as follows:

GPIO_setPadConfig(162, GPIO_PIN_TYPE_STD);
GPIO_setPinConfig(GPIO_162_GPIO162);
GPIO_setDirectionMode(162, GPIO_DIR_MODE_OUT);
GPIO_setMasterCore(162, GPIO_CORE_CPU2);

However running the GPIO_writePin() function from core 2 doesn't seem to work. I tried a few other pins, and also from core 1 and that doesn't seem to work anymore either.

I then decided to try the included LED demo to no success (see below). I set it up so I could use build configurations and defined symbols to target the different cores from the same project (hence the preprocessor define gating). 

#include "driverlib.h"
#include "device.h"

#define DEVICE_GPIO_PIN_LED1 59
#define DEVICE_GPIO_PIN_LED2 162
#ifdef CPU1
void main(void)
{
    //
    // Initialize device clock and peripherals
    //
    Device_init();

    //
    // Initialize GPIO and configure the GPIO pin as a push-pull output
    //
    Device_initGPIO();
    GPIO_setPadConfig(DEVICE_GPIO_PIN_LED1, GPIO_PIN_TYPE_STD);
    GPIO_setDirectionMode(DEVICE_GPIO_PIN_LED1, GPIO_DIR_MODE_OUT);
    GPIO_setPadConfig(DEVICE_GPIO_PIN_LED2, GPIO_PIN_TYPE_STD);
    GPIO_setDirectionMode(DEVICE_GPIO_PIN_LED2, GPIO_DIR_MODE_OUT);

    //
    // Configure CPU2 to control the LED GPIO
    //
    GPIO_setMasterCore(DEVICE_GPIO_PIN_LED2, GPIO_CORE_CPU2);

    //
    // Initialize PIE and clear PIE registers. Disables CPU interrupts.
    //
    Interrupt_initModule();

    //
    // Initialize the PIE vector table with pointers to the shell Interrupt
    // Service Routines (ISR).
    //
    Interrupt_initVectorTable();

    //
    // Enable Global Interrupt (INTM) and realtime interrupt (DBGM)
    //
    EINT;
    ERTM;

    //
    // Loop Forever
    //
    for(;;)
    {
        //
        // Turn on LED
        //
        GPIO_writePin(DEVICE_GPIO_PIN_LED1, 0);

        //
        // Delay for a bit.
        //
        DEVICE_DELAY_US(500000);

        //
        // Turn off LED
        //
        GPIO_writePin(DEVICE_GPIO_PIN_LED1, 1);

        //
        // Delay for a bit.
        //
        DEVICE_DELAY_US(500000);
    }
}
#endif
#ifdef CPU2
void main(void)
{
    //
    // Initialize device clock and peripherals
    //
    Device_init();

    //
    // Initialize GPIO and configure the GPIO pin as a push-pull output
    //
    // This is configured by CPU1

    //
    // Initialize PIE and clear PIE registers. Disables CPU interrupts.
    //
    Interrupt_initModule();

    //
    // Initialize the PIE vector table with pointers to the shell Interrupt
    // Service Routines (ISR).
    //
    Interrupt_initVectorTable();

    //
    // Enable Global Interrupt (INTM) and realtime interrupt (DBGM)
    //
    EINT;
    ERTM;

    //
    // Loop Forever
    //
    for(;;)
    {
        //
        // Turn on LED
        //
        GPIO_writePin(DEVICE_GPIO_PIN_LED2, 0);

        //
        // Delay for a bit.
        //
        DEVICE_DELAY_US(500000);

        //
        // Turn off LED
        //
        GPIO_writePin(DEVICE_GPIO_PIN_LED2, 1);

        //
        // Delay for a bit.
        //
        DEVICE_DELAY_US(500000);
    }
}
#endif

I have the memory map setup so that CPU1 is using GS0 as its .sysmem section and CPU2 is using GS1 as its .system section, if that's worth anything. 

Any pointers would be greatly appreciated.

  • Hi,

    Your code looks good, it should work. I tested on my setup with LED1 changed to 31, and LED2 changed to 34 as I am using Launchpad. I can see both LEDs blinking properly.

    Is this your custom board or you are controlCARD? if you are using Launchpad or controlCARD, you can confirm the same by changing LED1 and LED2 to 31 and 34 respectively.

    If it is custom board, and watching the line manually, you can test it using GpioReg in register window.

  • My target is one of the controlCARDs, but I just now tested on a Launchpad as well to no success. Can you share your memory map files (.cmd)? I may have messed mine up:

    CPU1:

    MEMORY
    {
    PAGE 0 :  /* Program Memory */
              /* Memory (RAM/FLASH) blocks can be moved to PAGE1 for data allocation */
              /* BEGIN is used for the "boot to Flash" bootloader mode   */
    
       BEGIN           	: origin = 0x080000, length = 0x000002
       RAMM0           	: origin = 0x000122, length = 0x0002DE
       RAMD0           	: origin = 0x00B000, length = 0x000800
       RAMLS0          	: origin = 0x008000, length = 0x000800
       RAMLS1          	: origin = 0x008800, length = 0x000800
       RAMLS2      		: origin = 0x009000, length = 0x000800
       RAMLS3      		: origin = 0x009800, length = 0x000800
       RAMLS4      		: origin = 0x00A000, length = 0x000800
       RAMGS14          : origin = 0x01A000, length = 0x001000     /* Only Available on F28379D, F28377D, F28375D devices. Remove line on other devices. */
       RAMGS15          : origin = 0x01B000, length = 0x000FF8     /* Only Available on F28379D, F28377D, F28375D devices. Remove line on other devices. */
    
    //   RAMGS15_RSVD     : origin = 0x01BFF8, length = 0x000008    /* Reserve and do not use for code as per the errata advisory "Memory: Prefetching Beyond Valid Memory" */
    
       RESET           	: origin = 0x3FFFC0, length = 0x000002
    
       /* Flash sectors */
       FLASHA           : origin = 0x080002, length = 0x001FFE	/* on-chip Flash */
       FLASHB           : origin = 0x082000, length = 0x002000	/* on-chip Flash */
       FLASHC           : origin = 0x084000, length = 0x002000	/* on-chip Flash */
       FLASHD           : origin = 0x086000, length = 0x002000	/* on-chip Flash */
       FLASHE           : origin = 0x088000, length = 0x008000	/* on-chip Flash */
       FLASHF           : origin = 0x090000, length = 0x008000	/* on-chip Flash */
       FLASHG           : origin = 0x098000, length = 0x008000	/* on-chip Flash */
       FLASHH           : origin = 0x0A0000, length = 0x008000	/* on-chip Flash */
       FLASHI           : origin = 0x0A8000, length = 0x008000	/* on-chip Flash */
       FLASHJ           : origin = 0x0B0000, length = 0x008000	/* on-chip Flash */
       FLASHK           : origin = 0x0B8000, length = 0x002000	/* on-chip Flash */
       FLASHL           : origin = 0x0BA000, length = 0x002000	/* on-chip Flash */
       FLASHM           : origin = 0x0BC000, length = 0x002000	/* on-chip Flash */
       FLASHN           : origin = 0x0BE000, length = 0x001FF0	/* on-chip Flash */
    
    //   FLASHN_RSVD     : origin = 0x0BFFF0, length = 0x000010    /* Reserve and do not use for code as per the errata advisory "Memory: Prefetching Beyond Valid Memory" */
    
    PAGE 1 : /* Data Memory */
             /* Memory (RAM/FLASH) blocks can be moved to PAGE0 for program allocation */
    
       BOOT_RSVD       : origin = 0x000002, length = 0x000121     /* Part of M0, BOOT rom will use this for stack */
       RAMM1           : origin = 0x000400, length = 0x0003F8     /* on-chip RAM block M1 */
    //   RAMM1_RSVD      : origin = 0x0007F8, length = 0x000008     /* Reserve and do not use for code as per the errata advisory "Memory: Prefetching Beyond Valid Memory" */
       RAMD1           : origin = 0x00B800, length = 0x000800
    
       RAMLS5      : origin = 0x00A800, length = 0x000800
    
       RAMGS0      : origin = 0x00C000, length = 0x001000
       RAMGS1      : origin = 0x00D000, length = 0x001000
       RAMGS2      : origin = 0x00E000, length = 0x001000
       RAMGS3      : origin = 0x00F000, length = 0x001000
       RAMGS4      : origin = 0x010000, length = 0x001000
       RAMGS5      : origin = 0x011000, length = 0x001000
       RAMGS6      : origin = 0x012000, length = 0x001000
       RAMGS7      : origin = 0x013000, length = 0x001000
       RAMGS8      : origin = 0x014000, length = 0x001000
       RAMGS9      : origin = 0x015000, length = 0x001000
       RAMGS10     : origin = 0x016000, length = 0x001000
    
    //   RAMGS11     : origin = 0x017000, length = 0x000FF8   /* Uncomment for F28374D, F28376D devices */
    
    //   RAMGS11_RSVD : origin = 0x017FF8, length = 0x000008    /* Reserve and do not use for code as per the errata advisory "Memory: Prefetching Beyond Valid Memory" */
    
       RAMGS11     : origin = 0x017000, length = 0x001000     /* Only Available on F28379D, F28377D, F28375D devices. Remove line on other devices. */
       RAMGS12     : origin = 0x018000, length = 0x001000     /* Only Available on F28379D, F28377D, F28375D devices. Remove line on other devices. */
       RAMGS13     : origin = 0x019000, length = 0x001000     /* Only Available on F28379D, F28377D, F28375D devices. Remove line on other devices. */
    
       CPU2TOCPU1RAM   : origin = 0x03F800, length = 0x000400
       CPU1TOCPU2RAM   : origin = 0x03FC00, length = 0x000400
    }
    
    SECTIONS
    {
       /* Allocate program areas: */
       .cinit              : > FLASHA      PAGE = 0, ALIGN(8)
       .text               : >> FLASHB | FLASHC | FLASHD | FLASHE      PAGE = 0, ALIGN(8)
       codestart           : > BEGIN       PAGE = 0, ALIGN(8)
       /* Allocate uninitalized data sections: */
       .stack              : > RAMM1       PAGE = 1
       .switch             : > FLASHB      PAGE = 0, ALIGN(8)
       .reset              : > RESET,      PAGE = 0, TYPE = DSECT /* not used, */
    
    #if defined(__TI_EABI__)
       .init_array         : > FLASHB,       PAGE = 0,       ALIGN(8)
       .bss                : > RAMLS5,       PAGE = 1
       .bss:output         : > RAMLS3,       PAGE = 0
       .bss:cio            : > RAMLS5,       PAGE = 1
       .data               : > RAMLS5,       PAGE = 1
       .sysmem             : > RAMGS1,       PAGE = 1
       /* Initalized sections go in Flash */
       .const              : > FLASHF,       PAGE = 0,       ALIGN(8)
    #else
       .pinit              : > FLASHB,       PAGE = 0,       ALIGN(8)
       .ebss               : >> RAMLS5 | RAMGS0 | RAMGS1,    PAGE = 1
       .esysmem            : > RAMLS5,       PAGE = 1
       .cio                : > RAMLS5,       PAGE = 1
       /* Initalized sections go in Flash */
       .econst             : >> FLASHF      PAGE = 0, ALIGN(8)
    #endif
    
       Filter_RegsFile     : > RAMGS0,	   PAGE = 1
    
       SHARERAMGS0		: > RAMGS0,		PAGE = 1
       SHARERAMGS1		: > RAMGS1,		PAGE = 1
       ramgs0           : > RAMGS0,     PAGE = 1
       ramgs1           : > RAMGS1,     PAGE = 1
    
    #ifdef __TI_COMPILER_VERSION__
        #if __TI_COMPILER_VERSION__ >= 15009000
            #if defined(__TI_EABI__)
                .TI.ramfunc : {} LOAD = FLASHD,
                                     RUN = RAMLS0,
                                     LOAD_START(RamfuncsLoadStart),
                                     LOAD_SIZE(RamfuncsLoadSize),
                                     LOAD_END(RamfuncsLoadEnd),
                                     RUN_START(RamfuncsRunStart),
                                     RUN_SIZE(RamfuncsRunSize),
                                     RUN_END(RamfuncsRunEnd),
                                     PAGE = 0, ALIGN(8)
            #else
                .TI.ramfunc : {} LOAD = FLASHD,
                                 RUN = RAMLS0,
                                 LOAD_START(_RamfuncsLoadStart),
                                 LOAD_SIZE(_RamfuncsLoadSize),
                                 LOAD_END(_RamfuncsLoadEnd),
                                 RUN_START(_RamfuncsRunStart),
                                 RUN_SIZE(_RamfuncsRunSize),
                                 RUN_END(_RamfuncsRunEnd),
                                 PAGE = 0, ALIGN(8)
            #endif
        #else
       ramfuncs            : LOAD = FLASHD,
                             RUN = RAMLS0,
                             LOAD_START(_RamfuncsLoadStart),
                             LOAD_SIZE(_RamfuncsLoadSize),
                             LOAD_END(_RamfuncsLoadEnd),
                             RUN_START(_RamfuncsRunStart),
                             RUN_SIZE(_RamfuncsRunSize),
                             RUN_END(_RamfuncsRunEnd),
                             PAGE = 0, ALIGN(8)
        #endif
    
    #endif
    
       /* The following section definitions are required when using the IPC API Drivers */
        GROUP : > CPU1TOCPU2RAM, PAGE = 1
        {
            PUTBUFFER
            PUTWRITEIDX
            GETREADIDX
        }
    
        GROUP : > CPU2TOCPU1RAM, PAGE = 1
        {
            GETBUFFER :    TYPE = DSECT
            GETWRITEIDX :  TYPE = DSECT
            PUTREADIDX :   TYPE = DSECT
        }
    
       /* The following section definition are for SDFM examples */
       Filter1_RegsFile : > RAMGS1,	PAGE = 1, fill=0x1111
       Filter2_RegsFile : > RAMGS2,	PAGE = 1, fill=0x2222
       Filter3_RegsFile : > RAMGS3,	PAGE = 1, fill=0x3333
       Filter4_RegsFile : > RAMGS4,	PAGE = 1, fill=0x4444
       Difference_RegsFile : >RAMGS5, 	PAGE = 1, fill=0x3333
    }
    

    CPU2:

    MEMORY
    {
    PAGE 0 :  /* Program Memory */
              /* Memory (RAM/FLASH) blocks can be moved to PAGE1 for data allocation */
              /* BEGIN is used for the "boot to Flash" bootloader mode   */
    
       BEGIN           	: origin = 0x080000, length = 0x000002
       RAMM0           	: origin = 0x000122, length = 0x0002DE
       RAMD0           	: origin = 0x00B000, length = 0x000800
       RAMLS0          	: origin = 0x008000, length = 0x000800
       RAMLS1          	: origin = 0x008800, length = 0x000800
       RAMLS2      		: origin = 0x009000, length = 0x000800
       RAMLS3      		: origin = 0x009800, length = 0x000800
       RAMLS4      		: origin = 0x00A000, length = 0x000800
       RAMGS14          : origin = 0x01A000, length = 0x001000     /* Only Available on F28379D, F28377D, F28375D devices. Remove line on other devices. */
       RAMGS15          : origin = 0x01B000, length = 0x000FF8     /* Only Available on F28379D, F28377D, F28375D devices. Remove line on other devices. */
    
    //   RAMGS15_RSVD     : origin = 0x01BFF8, length = 0x000008    /* Reserve and do not use for code as per the errata advisory "Memory: Prefetching Beyond Valid Memory" */
    
       RESET           	: origin = 0x3FFFC0, length = 0x000002
    
       /* Flash sectors */
       FLASHA           : origin = 0x080002, length = 0x001FFE	/* on-chip Flash */
       FLASHB           : origin = 0x082000, length = 0x002000	/* on-chip Flash */
       FLASHC           : origin = 0x084000, length = 0x002000	/* on-chip Flash */
       FLASHD           : origin = 0x086000, length = 0x002000	/* on-chip Flash */
       FLASHE           : origin = 0x088000, length = 0x008000	/* on-chip Flash */
       FLASHF           : origin = 0x090000, length = 0x008000	/* on-chip Flash */
       FLASHG           : origin = 0x098000, length = 0x008000	/* on-chip Flash */
       FLASHH           : origin = 0x0A0000, length = 0x008000	/* on-chip Flash */
       FLASHI           : origin = 0x0A8000, length = 0x008000	/* on-chip Flash */
       FLASHJ           : origin = 0x0B0000, length = 0x008000	/* on-chip Flash */
       FLASHK           : origin = 0x0B8000, length = 0x002000	/* on-chip Flash */
       FLASHL           : origin = 0x0BA000, length = 0x002000	/* on-chip Flash */
       FLASHM           : origin = 0x0BC000, length = 0x002000	/* on-chip Flash */
       FLASHN           : origin = 0x0BE000, length = 0x001FF0	/* on-chip Flash */
    
    //   FLASHN_RSVD     : origin = 0x0BFFF0, length = 0x000010    /* Reserve and do not use for code as per the errata advisory "Memory: Prefetching Beyond Valid Memory" */
    
    PAGE 1 : /* Data Memory */
             /* Memory (RAM/FLASH) blocks can be moved to PAGE0 for program allocation */
    
       BOOT_RSVD       : origin = 0x000002, length = 0x000121     /* Part of M0, BOOT rom will use this for stack */
       RAMM1           : origin = 0x000400, length = 0x0003F8     /* on-chip RAM block M1 */
    //   RAMM1_RSVD      : origin = 0x0007F8, length = 0x000008     /* Reserve and do not use for code as per the errata advisory "Memory: Prefetching Beyond Valid Memory" */
       RAMD1           : origin = 0x00B800, length = 0x000800
    
       RAMLS5      : origin = 0x00A800, length = 0x000800
    
       RAMGS0      : origin = 0x00C000, length = 0x001000
       RAMGS1      : origin = 0x00D000, length = 0x001000
       RAMGS2      : origin = 0x00E000, length = 0x001000
       RAMGS3      : origin = 0x00F000, length = 0x001000
       RAMGS4      : origin = 0x010000, length = 0x001000
       RAMGS5      : origin = 0x011000, length = 0x001000
       RAMGS6      : origin = 0x012000, length = 0x001000
       RAMGS7      : origin = 0x013000, length = 0x001000
       RAMGS8      : origin = 0x014000, length = 0x001000
       RAMGS9      : origin = 0x015000, length = 0x001000
       RAMGS10     : origin = 0x016000, length = 0x001000
    
    //   RAMGS11     : origin = 0x017000, length = 0x000FF8   /* Uncomment for F28374D, F28376D devices */
    
    //   RAMGS11_RSVD : origin = 0x017FF8, length = 0x000008    /* Reserve and do not use for code as per the errata advisory "Memory: Prefetching Beyond Valid Memory" */
    
       RAMGS11     : origin = 0x017000, length = 0x001000     /* Only Available on F28379D, F28377D, F28375D devices. Remove line on other devices. */
       RAMGS12     : origin = 0x018000, length = 0x001000     /* Only Available on F28379D, F28377D, F28375D devices. Remove line on other devices. */
       RAMGS13     : origin = 0x019000, length = 0x001000     /* Only Available on F28379D, F28377D, F28375D devices. Remove line on other devices. */
    
       CPU2TOCPU1RAM   : origin = 0x03F800, length = 0x000400
       CPU1TOCPU2RAM   : origin = 0x03FC00, length = 0x000400
    }
    
    SECTIONS
    {
       /* Allocate program areas: */
       .cinit              : > FLASHA      PAGE = 0, ALIGN(8)
       .text               : >> FLASHB | FLASHC | FLASHD | FLASHE      PAGE = 0, ALIGN(8)
       codestart           : > BEGIN       PAGE = 0, ALIGN(8)
       /* Allocate uninitalized data sections: */
       .stack              : > RAMM1       PAGE = 1
       .switch             : > FLASHB      PAGE = 0, ALIGN(8)
       .reset              : > RESET,      PAGE = 0, TYPE = DSECT /* not used, */
    
    #if defined(__TI_EABI__)
       .init_array         : > FLASHB,       PAGE = 0,       ALIGN(8)
       .bss                : > RAMLS5,       PAGE = 1
       .bss:output         : > RAMLS3,       PAGE = 0
       .bss:cio            : > RAMLS5,       PAGE = 1
       .data               : > RAMLS5,       PAGE = 1
       .sysmem             : > RAMGS2,       PAGE = 1
       /* Initalized sections go in Flash */
       .const              : > FLASHF,       PAGE = 0,       ALIGN(8)
    #else
       .pinit              : > FLASHB,       PAGE = 0,       ALIGN(8)
       .ebss               : >> RAMLS5 | RAMGS0 | RAMGS1,    PAGE = 1
       .esysmem            : > RAMLS5,       PAGE = 1
       .cio                : > RAMLS5,       PAGE = 1
       /* Initalized sections go in Flash */
       .econst             : >> FLASHF      PAGE = 0, ALIGN(8)
    #endif
    
       Filter_RegsFile     : > RAMGS0,	   PAGE = 1
    
       SHARERAMGS0		: > RAMGS0,		PAGE = 1
       SHARERAMGS1		: > RAMGS1,		PAGE = 1
       ramgs0           : > RAMGS0,     PAGE = 1
       ramgs1           : > RAMGS1,     PAGE = 1
    
    #ifdef __TI_COMPILER_VERSION__
        #if __TI_COMPILER_VERSION__ >= 15009000
            #if defined(__TI_EABI__)
                .TI.ramfunc : {} LOAD = FLASHD,
                                     RUN = RAMLS0,
                                     LOAD_START(RamfuncsLoadStart),
                                     LOAD_SIZE(RamfuncsLoadSize),
                                     LOAD_END(RamfuncsLoadEnd),
                                     RUN_START(RamfuncsRunStart),
                                     RUN_SIZE(RamfuncsRunSize),
                                     RUN_END(RamfuncsRunEnd),
                                     PAGE = 0, ALIGN(8)
            #else
                .TI.ramfunc : {} LOAD = FLASHD,
                                 RUN = RAMLS0,
                                 LOAD_START(_RamfuncsLoadStart),
                                 LOAD_SIZE(_RamfuncsLoadSize),
                                 LOAD_END(_RamfuncsLoadEnd),
                                 RUN_START(_RamfuncsRunStart),
                                 RUN_SIZE(_RamfuncsRunSize),
                                 RUN_END(_RamfuncsRunEnd),
                                 PAGE = 0, ALIGN(8)
            #endif
        #else
       ramfuncs            : LOAD = FLASHD,
                             RUN = RAMLS0,
                             LOAD_START(_RamfuncsLoadStart),
                             LOAD_SIZE(_RamfuncsLoadSize),
                             LOAD_END(_RamfuncsLoadEnd),
                             RUN_START(_RamfuncsRunStart),
                             RUN_SIZE(_RamfuncsRunSize),
                             RUN_END(_RamfuncsRunEnd),
                             PAGE = 0, ALIGN(8)
        #endif
    
    #endif
    
       /* The following section definitions are required when using the IPC API Drivers */
        GROUP : > CPU1TOCPU2RAM, PAGE = 1
        {
            PUTBUFFER
            PUTWRITEIDX
            GETREADIDX
        }
    
        GROUP : > CPU2TOCPU1RAM, PAGE = 1
        {
            GETBUFFER :    TYPE = DSECT
            GETWRITEIDX :  TYPE = DSECT
            PUTREADIDX :   TYPE = DSECT
        }
    
       /* The following section definition are for SDFM examples */
       Filter1_RegsFile : > RAMGS1,	PAGE = 1, fill=0x1111
       Filter2_RegsFile : > RAMGS2,	PAGE = 1, fill=0x2222
       Filter3_RegsFile : > RAMGS3,	PAGE = 1, fill=0x3333
       Filter4_RegsFile : > RAMGS4,	PAGE = 1, fill=0x4444
       Difference_RegsFile : >RAMGS5, 	PAGE = 1, fill=0x3333
    }
    
    
    

    I want to have each cores heap memory in the shared memory segments (GSx) so that I can have read access from the other core, so I made tweaks to accommodate that. 

  • Owen,

    Looking at the linker command file, it looks like you are booting from flash. You must include _FLASH predefined symbol for cpu1 and cpu2 project and then build the binaries for cpu1 and cpu2. It should work with that.  I just validated it with your code and your linker command file on Launchpad.

    Please let me know if it resolves your issue.

  • Any update on this? Are you able to resolve the issue?

  • Santosh,

    I just checked now. _FLASH is defined for both of my build configurations (CPU1_FLASH, CPU2_FLASH). 

  • Owen,

    I just validated this project on Launchpad. It is your code and your linker command file. The only changes is that I have commented following lines, so it uses GPIO31 and GPIO34 which are default.

    //#define DEVICE_GPIO_PIN_LED1 59
    //#define DEVICE_GPIO_PIN_LED2 162
  • Thanks for sending this over. I had to make some tweaks to get it to build:

    1. Changed target device from 8377D to 8379D

    2. Change the C2000 paths

    3. Change the driverlib.lib path 

    4. Add the C2000 3.3.0.00 listing in the Resource > CCS General > Products tab 

    What is your sequence for flashing the device? If I flash CPU1, the light on the launchpad blinks. If I then flash CPU2, it seems CPU1 is halted and the light stops flashing. CPU2's light never blinks. 

  • Owen,

    I launch the target configuration, connect CPU1 and CPU2.

    then I load CPU1, after flashing it is halted at main() function. Then I load CPU2, after flashing it is waiting on main() function.

    Run CPU1, blue LED starts blinking

    Run CPU2, Blue and Red LED start blinking.

    Can you try C2000ware DriverLib IPC example for led_toggle? Please use the CPU1_FLASH configuration. Let's see if that works on your setup. It is very close to your code and linker command file.

  • Santosh,

    I have it working now. I set the DEBUG flag in the build settings. I launched the target configuration, flashed CPU1 (halted at main), then flashed CPU2 (halted at main). I let CPU1 run first, and then let CPU2 run. Both lines are toggling now. 

  • Great. Thanks for confirming

  • I was finally able to figure out the difference between our build settings that was causing issues. For some reason, switch the binary output format from eabi to legacy coff. 

    Any thoughts on why this would matter? 

  • Owen,

    It should not matter. Both output format should work. I just changed the output format of COFF for both projects and I tested it, it is working fine.