Part Number: TMS320F28388S
Dear Team,
In the errata "SPRZ458C – MAY 2019 – REVISED NOVEMBER 2020" for the TMS320F2838x series there is point relating to the ESC.
It states that:
"The EtherCAT Slave Controller Distributed Clocking registers responsible for offset and
drift compensation are only writable by the host CPU and not by the EtherCAT master.
Because of this, Distributed Clocking Mode is not supported on the affected revision."
Can you further clarify on this matter? We are building some high performance motion drivers and need to understand the implications of this.
I am running the CiA402 example solution provided in the examples. In the Twincat, I am operating in the DC-Synchon mode. In the CSV mode, I am able to set the Target velocity object, and the corresponding Actual Position object is getting updated (looking at the code, it means that the bDcSyncActive flag is active, and the u32CycleTime for the object is set correctly). Additionally with the debugger, I also see that the Sync0_ISR is getting triggered.
Everything seems to be running normally. But it worries me about this passage indicated in the errata.
Please advise.
Warm Regards,
CJ
