TMS320F28069: F28069 DMA/MCBSP stop work under EMI test

Jane,

The value of "1" in bit 10 isn't a concern.  This was a function that was removed/unsupported during evaluation of the DMA module.  I looks like the logic is still there, but we don't support the use of it, and in this case there is no meaning to that bit being set to the issue customer has.

From the SPCR1 register it is indicating that the RSYNCERR and RFULL bits are high, meaning there has been both a sync error as well as the read register is full and not read from the DMA.

My thought is that perhaps the slave enable signal coming into the C2000(on the FSK signal) has noise from the EMI test, and this causes a frame sync issue if it is driven mid transmission(or when no transmission should be taking place to the C2000).

I'd like to see if we can enable some extra qualification on this signal to remove the noise from the EMI test.  For below code I'm going to assume customer is using GPIO23 for the MFSXA signal, but if they are using another GPIO they can just replace it in the code below (they will need to verify the GPIO is in the correct QUALPRD group.

Since this is qualified to SYSCLK, I don't anticipate the lag causing issues with the McBSP which should be clocked at a much lower rate.  Let's try either 3 or 6 samples and see if that fixes the issue.

Best,
Matthew

    EALLOW;
    GpioCtrlRegs.GPACTRL.bit.QUALPRD2 = 0;  //set the qual period = to SYSCLK
    GpioCtrlRegs.GPAQSEL2.bit.GPIO23 = 1;   //set the pin qualification to 3 samples
//  Comment the above and uncomment the below to use 6 samples for the qualification
//  GpioCtrlRegs.GPAQSEL2.bit.GPIO23 = 2;   //set the pin qualification to 6 samples
    EDIS;