Hi all,
I am trying to use the McBSP peripherial on an TMS320C28346 DIM168 Evaluation Board to interface to an Analog Devices AD7655 ADC.
The ADC has several serial communication modes. One of them is SPI-Master. So I configured the McBsp to run in SPI slave mode.
The ADC is supplying the CS (on the DSP: FSX) signal for framing the serial data.
The ADC is sending two 16-bit words each seperatly framed by CS going low in front of the 16-bit serial data.
My Problem seems to be that the first bit (the MSB) is not received.
I am looking at the serial data with a DSO.
For example the ADC is sending 0x8080 (a value which I decoded "by hand" from the scope display), then the DRR1register is reading 0x0100.
In my opinion this can only be when the first bit is not received an the following low signal level (after the SPI-Clock stopped toggling ?!) is sampled and shifted into DRR1.
The interessting thing is that if I reduce the signal speed (Problem ocurres at 18MHz serial clock) to half of it (9Mhz) every thing works like expected. (In accordance to the above given example, DRR1 would read 0x8080 after a word was sent from the ADC)
I also tried the different clockstop modes (page 67 on the McBSP manual) with no differing result.
I also was worried that the CS signal from the ADC is violating a timing requirement by getting low just about 15ns before SCLK starts toggleing but I found a value of 4ns of setup time for the FSX signal when an external clock is applied.
My McBsp config is:
// McBSP register settings in SPI slave mode
McbspaRegs.SPCR2.all=0x0000; // Reset FS generator, sample rate generator & transmitter
McbspaRegs.SPCR1.all=0x0000; // Reset Receiver, Right justify word, Digital loopback dis.
McbspaRegs.PCR.all=0x0008; //(CLKXM=CLKRM=FSXM=FSRM= 0, FSXP = 1)
McbspaRegs.SPCR1.bit.CLKSTP = 2; // Together with CLKXP/CLKRP determines clocking scheme
McbspaRegs.SPCR2.bit.FREE = 0;
McbspaRegs.PCR.bit.CLKXP = 0; // CPOL = 0, CPHA = 0 receive data on falling edge of SCLK
McbspaRegs.PCR.bit.CLKRP = 0;
McbspaRegs.RCR2.bit.RDATDLY=0; // FSX setup time 1 in master mode. 0 for slave mode (Receive)
McbspaRegs.XCR2.bit.XDATDLY=0; // FSX setup time 1 in master mode. 0 for slave mode (Transmit)
McbspaRegs.RCR1.bit.RWDLEN1=1; // 16-bit word
McbspaRegs.XCR1.bit.XWDLEN1=1; // 16-bit word
//McbspaRegs.RCR2.bit.RFIG = 1;
McbspaRegs.SRGR2.all=0x2000; // CLKSM=1, FPER = 1 CLKG periods
McbspaRegs.SRGR1.all=0x0000; // Frame Width = 1 CLKG period, CLKGDV=1 for slave
McbspaRegs.SPCR2.bit.GRST=1; // Enable the sample rate generator
delay_loop(); // Wait at least 2 SRG clock cycles
McbspaRegs.SPCR2.bit.XRST=1; // Release TX from Reset
McbspaRegs.SPCR1.bit.RRST=1; // Release RX from Reset
McbspaRegs.SPCR2.bit.FRST=1; // Frame Sync Generator reset
Any help or suggestions would be very appreciated.
- Bernhard Kiesbauer
