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Hi experts,
My customer use SINCFAST filter, OSR=128, Sdfm1Regs.SDDPARM2.bit.SH=1. When input of AMC1306 is -250mV~250mV, hey found the data fluctuates greatly. They thought that for SINCFAST filter, OSR=128, the data scope is -32768~32767, within the 16-bit data range, the shift registers are not required to be operated. Is it right?
The second issue is when selecting the SINC3 filter, the data fluctuates significantly under the same conditions as SINCFAST filter type. Here is the measured result:
When the SINC3 filter is selected, OSR=32, the shift register 0, the amc1306 modulator input 250mV signal, the theoretical data is 25598, but the actual data range is form 28389 to 28553.
Here is the code:
EALLOW;
EPwm5Regs.TBPHS.all = 0;
EPwm5Regs.TBCTL.all = 0xc000;
EPwm5Regs.CMPCTL.all = 0x0;
EPwm5Regs.CMPCTL2.all = 0x0;
EPwm5Regs.AQCSFRC.all = 0x0; //Force Disable
/*Action-Qualifier Output A Control Register*/
EPwm5Regs.AQCTLA.all = 0x0003;
/*Action-Qualifier Output A2 Control Register*/
EPwm5Regs.AQCTLA2.all = 0;
/*Do nothing*/
/*Action-Qualifier Output B Control Register*/
EPwm5Regs.AQCTLB.all = 0;
/*Do nothing*/
/*Action-Qualifier Output B2 Control Register*/
EPwm5Regs.AQCTLB2.all = 0;
/*Do nothing*/
/*Dead-Band Generator Control Register*/
EPwm5Regs.DBCTL.all = 0x0007;
/*Event-Trigger Selection Register*/
EPwm5Regs.ETSEL.all = 0x0;
/*Event-Trigger Prescale Register*/
EPwm5Regs.ETPS.all = 0x0;
/*Time-Base Period Register*/
//EPwm5Regs.TBPRD = 4; // 10M 100M/10M/2 - 1 = 4
EPwm5Regs.TBPRD = 2; // 16.67M 100M/(2 + 1)/2 = 16M
//IU sigma-delta ADC
Sdfm1Regs.SDDFPARM2.bit.DOSR = 128;
Sdfm1Regs.SDDFPARM2.bit.SST = 0;
Sdfm1Regs.SDDFPARM2.bit.FEN = 1;
Sdfm1Regs.SDDPARM2.bit.DR = 0;
Sdfm1Regs.SDDPARM2.bit.SH = 0;
//IW sigma-detal ADC
Sdfm1Regs.SDDFPARM4.bit.DOSR = 128;
Sdfm1Regs.SDDFPARM4.bit.SST = 0;
Sdfm1Regs.SDDFPARM4.bit.FEN = 1;
Sdfm1Regs.SDDPARM4.bit.DR = 0;
Sdfm1Regs.SDDPARM4.bit.SH = 0;
//Comparator (Secondary) Filter Unit Config
//0-32768
Sdfm1Regs.SDCPARM2.bit.COSR = 31;
//Sinc3
Sdfm1Regs.SDCPARM2.bit.CS1_CS0 = 3;
Sdfm1Regs.SDCPARM2.bit.CEN = 1;
Sdfm1Regs.SDCPARM2.bit.IEH = 1;
Sdfm1Regs.SDCPARM2.bit.IEL = 1;
Sdfm1Regs.SDCPARM4.bit.COSR = 31;
Sdfm1Regs.SDCPARM4.bit.CS1_CS0 = 3;
Sdfm1Regs.SDCPARM4.bit.CEN = 1;
Sdfm1Regs.SDCPARM4.bit.IEH = 1;
Sdfm1Regs.SDCPARM4.bit.IEL = 1;
Sdfm1Regs.SDMFILEN.bit.MFE = 1;
Sdfm1Regs.SDCTL.bit.MIE = 1;
EPwmXbarRegs.TRIP4MUX16TO31CFG.bit.MUX18 = 1;
EPwmXbarRegs.TRIP4MUX16TO31CFG.bit.MUX22 = 1;
EPwmXbarRegs.TRIP4MUXENABLE.bit.MUX18 = 1;
EPwmXbarRegs.TRIP4MUXENABLE.bit.MUX22 = 1;
Sdfm1Regs.SDCMPH2.bit.HLT = 24000;
Sdfm1Regs.SDCMPL2.bit.LLT = 10000;
Sdfm1Regs.SDCMPH4.bit.HLT = 24000;
Sdfm1Regs.SDCMPL4.bit.LLT = 10000;
EDIS;
EALLOW;
Sdfm1Regs.SDIFLGCLR.bit.MIF = 1;
EDIS;
Zou,
Theoritical SDFM filter output calculation information just got recently updated in F280049 TRM and is awaiting release. But, fortunately, the same information is available in F28388d TRM. https://www.ti.com/lit/pdf/spruii0.
Please check "Theoretical SDFM Filter Output" section in SDFM chapter. Using, these formulae, I have calculated theoretical filter output for comparator filter and data filter with the configuration mentioned above.
In the above post,
My customer use SINCFAST filter, OSR=128, Sdfm1Regs.SDDPARM2.bit.SH=1. When input of AMC1306 is -250mV~250mV, hey found the data fluctuates greatly. They thought that for SINCFAST filter, OSR=128, the data scope is -32768~32767, within the 16-bit data range, the shift registers are not required to be operated. Is it right?
You had mentioned that data filter output fluctuates greatly. You haven't mentioned the reading observed. With SincFast and DOSR = 128, you can expect around 12-bit of ENOB. If you operate SD-modulator within +/- 250mv range, you don't need to use shift registers.
When the SINC3 filter is selected, OSR=32, the shift register 0, the amc1306 modulator input 250mV signal, the theoretical data is 25598, but the actual data range is form 28389 to 28553.
Do you observe this on comparator filter (or) data filter?
Regards,
Manoj
Is that mean if I choose SINCFAST, DOSR=128, then the shift register should be set equal to 1?
When the SINC3 filter is selected, OSR=32, the shift register 0, the amc1306 modulator input 250mV signal, the theoretical data is 25598, but the actual data range is form 28389 to 28553.
Do you observe this on comparator filter (or) data filter?
This is data filter.
If the analog input to the modulator is within recommended +/- 250mv, then it is okay to set shift register to 0.
But, it is not within the recommended voltage range, then shift register value needs to be 1 for DOSR =128.
Regards,
Manoj
Did you ensure AMC1306 SD-modulator analog input is a steady 250mv?
SDFM is a digital filter. It just basically calculates filter output based on SD-modulated bit stream it receives from the SD-modulator. If you ensure analog input is steady and stable, you should get stable results.
Regards,
Manoj
But in TRM, there is a table(Table 17-4. Shift Control Bit Configuration Settings). According to the table, the shift register is set to be 1.
Yes. The input of modulator is steady. As I mentioned above, under the same condition, the output of SINCFAST is steady, but the output of SINC3 is unsteady. Is there any difference between the two types?
The table assumes that SD-modulator analog input can touch Vclipping voltage (+/-320mv). If customer ensures to keep within (+/- 250mv) then customer can get away without right shifting by 1 bit for Sincfast DOSR = 128
SINCFAST is steady, but the output of SINC3 is unsteady. Is there any difference between the two types?
SincFast and Sinc3 are two different type of low pass filters. Sinc3 generally provides higher ENOB with higher OSR settings.
Below is snippet from ADS1203 datasheet which graphically OSR vs ENOB
The question is the input of modulator is steady. As I mentioned above, under the same condition, the output of SINCFAST is steady, but the output of SINC3 is unsteady. Have you test before and compare both output? Do you know why under the same input, the output of SINCFAST is steady, but the output of SINC3 is unsteady?
Angelo,
Are you claiming the following:-
SincFast + DOSR = 128 - Stable results
Sinc3 + DOSR = 128 - Unstable results
Are you using 32-bit representation (or) 16 bit representation? Do you see the problem in both 32-bit and 16-bit representation? Are you using SDSYNC feature? If so, did you try disabling SDSYNC feature? Do you see the stable results when you disable SDSYNC feature?
Regards,
Manoj
Hi Manoj,
They use 16 bit, never try 32 bit. They also never enable SDSYNC.
Angelo,
Can you please confirm the filter settings? Also, can you ask the customer to try both Sincfast and Sinc3 filter in 32-bit mode?
Regards,
Manoj
Hi Manoj,
I have uploaded the codes, any other information needed? I will customer to try both Sincfast and Sinc3 filter in 32-bit mode.
Hi Manoj,
Both 16-bit and 3-bit mode, the fluctuating of SINC3 is more than SINCFAST. The SINCFAST filter fluctuates within the maximum of 4, and the SINC3 filter fluctuates approximately 30 maximum.
Angelo,
What is the OSR setting? If Sincfast provides better ENOB vs OSR performance than Sinc3 at lower OSR setting.
Regards,
Manoj
ENOB vs OSR performance difference between Sinc3 vs Sincfast is marginal with Sinc3 having small edge over SincFast.
If I were you I would stick to using 16 bit mode for SincFast (or) Sinc3.
For OSR = 128, SincFast you need to shift by 1
For OSR = 128, Sinc3 you need to shift by 7.
With OSR = 128 and Sinc3 you can expect 13 bit of ENOB. Sincfast should also be pretty close to that.
Regards,
Manoj