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TMS320F28384S: SDFM Timing Requirements.

Part Number: TMS320F28384S


Hi champs,

According to datasheet, the minimum data setup time(tsu) of SDFM ASYNC mode is 1 x tc(PLLRAWCLK) + 5 ns. If PLLRAWCLK is 200MHz, then the minimum setup time is 10 ns, right?

But in F2837xS/D datasheet, the SDFM ASYNC minimum setup time is 5 ns, what's the reason we have this difference between these two devices?

Another question is that we don't list timing requirement of SDFM 3-sample window mode, where can we find this information please?

Regards,

Luke

  • Luke,

    In F28384D, MAX PLLRAWCLK frequency = 400 MHz. So, this corresponds to tc(PLLRAWCLK) = 2.5ns

    So, 1 x tc(PLLRAWCLK) + 5 ns = 2.5ns + 5ns = 7.5ns

    But in F2837xS/D datasheet, the SDFM ASYNC minimum setup time is 5 ns, what's the reason we have this difference between these two devices?

    In F28384D device, we have added a new feature "Input Qualification" circuitry in SDFM module. This synchronizes SD-CLK and SD-DATA with respect to PLLRAWCLK. That is the reason why we have an extra tc(PLLRAWCLK) requirement.

    Another question is that we don't list timing requirement of SDFM 3-sample window mode, where can we find this information please?

    In F28384D device, we don't want customers to use 3-sample QUAL on SDFM pins and use "Input Qualification" circuitry in SDFM module. Please make sure to synchronize SD-CLK / SD-DATA with respect to PLLRAWCLK and ensure GPIO ASYNC option for SDFM pins.

    Regards,

    Manoj

  • Manoj,

    You mentioned make sure to synchronize SD-CLK / SD-DATA with respect to PLLRAWCLK.

    I don't get the point, what should I do please?

    Regards,

    Luke

  • In F2838x device, this should be your SDFM GPIO pin configuration:

    1) SD-Cx & SD-Dx pins should be configured in GPIO_ASYNC mode.

    2) Inside, SDFM module you need to make sure synchronize SD-Cx / SD-Dx with respect to PLLRAWCLK. with below configuration.

    SDCTLPARMx.SDDATASYNC = 1

    SDCTLPARMx.SDCLKSYNC  = 1

    Regards,

    Manoj