• State Resolved
  • Locked Locked
  • Replies 2 replies
  • Subscribers 82 subscribers
  • Views 355 views
  • Users 0 members are here
Support feedback
Options
Options
Related

This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

Original question:

Compiler: #define CPU_RATE

incompatible redefinition of macro "CPU_RATE"

Paul Ratcliffe
Prodigy 20 points
Other Parts Discussed in Thread: C2000WARE

I'm modifying the f2803x/c28/flash_programming example to change the clock speed to 20MHz to match our PCB design.

In DSP2803x_EXAMPLES_H I set the following:

// Defines
//
//#define DSP28_DIVSEL 0 // Enable /4 for SYSCLKOUT
//#define DSP28_DIVSEL 1 // Disable /4 for SYSCKOUT
#define DSP28_DIVSEL 2 // Enable /2 for SYSCLKOUT
//#define DSP28_DIVSEL 3 // Enable /1 for SYSCLKOUT

//#define DSP28_PLLCR 12 //Uncomment for 60 MHz devs [60 MHz=(10MHz * 12)/2]
//#define DSP28_PLLCR 11
//#define DSP28_PLLCR 10
//#define DSP28_PLLCR 9
//#define DSP28_PLLCR 8 //Uncomment for 40 MHz devs [40 MHz=(10MHz * 8)/2]
//#define DSP28_PLLCR 7
//#define DSP28_PLLCR 6
//#define DSP28_PLLCR 5
#define DSP28_PLLCR 4
//#define DSP28_PLLCR 3
//#define DSP28_PLLCR 2
//#define DSP28_PLLCR 1
//#define DSP28_PLLCR 0 // PLL is bypassed in this mode

//
//#define CPU_RATE 16.667L // for a 60MHz CPU clock speed (SYSCLKOUT)
//#define CPU_RATE 20.000L // for a 50MHz CPU clock speed (SYSCLKOUT)
//#define CPU_RATE 25.000L // for a 40MHz CPU clock speed (SYSCLKOUT)
//#define CPU_RATE 33.333L // for a 30MHz CPU clock speed (SYSCLKOUT)
//#define CPU_RATE 41.667L // for a 24MHz CPU clock speed (SYSCLKOUT)
#define CPU_RATE 50.000L // for a 20MHz CPU clock speed (SYSCLKOUT)
//#define CPU_RATE 66.667L // for a 15MHz CPU clock speed (SYSCLKOUT)
//#define CPU_RATE 100.000L // for a 10MHz CPU clock speed (SYSCLKOUT)

and in EXAMPLE_FLASH2803x_API_H I set:

//
//#define PLLCR_VALUE 0x000C // SYSCLKOUT = (OSCLK*12)/2
// #define PLLCR_VALUE 0x000B // SYSCLKOUT = (OSCLK*11)/2
// #define PLLCR_VALUE 0x000A // SYSCLKOUT = (OSCLK*10)/2
// #define PLLCR_VALUE 0x0009 // SYSCLKOUT = (OSCLK*9)/2
// #define PLLCR_VALUE 0x0008 // SYSCLKOUT = (OSCLK*8)/2
// #define PLLCR_VALUE 0x0007 // SYSCLKOUT = (OSCLK*7)/2
// #define PLLCR_VALUE 0x0006 // SYSCLKOUT = (OSCLK*6)/2
// #define PLLCR_VALUE 0x0005 // SYSCLKOUT = (OSCLK*5)/2
#define PLLCR_VALUE 0x0004 // SYSCLKOUT = (OSCLK*4)/2
// #define PLLCR_VALUE 0x0003 // SYSCLKOUT = (OSCLK*3)/2
// #define PLLCR_VALUE 0x0002 // SYSCLKOUT = (OSCLK*2)/2
// #define PLLCR_VALUE 0x0001 // SYSCLKOUT = (OSCLK*1)/2
// #define PLLCR_VALUE 0x0000 // SYSCLKOUT = (OSCLK)/2 (PLL Bypassed)

which I believe sets SYSCLK to 20MHz but when I build it I get the warning: 

Description Resource Path Location Type
incompatible redefinition of macro "CPU_RATE" (declared at line 87 of "C:\ti\c2000\C2000Ware_3_04_00_00\libraries\flash_api\f2803x\include\Flash2803x_API_Config.h") .ccsproject /Example_2803xFlashProgramming line 103, external location: C:\ti\c2000\C2000Ware_3_04_00_00\device_support\f2803x\common\include\DSP2803x_Examples.h C/C++ Problem

Can anyone point out what I have got wrong?

  • +1
    TI__Guru* 81990 points

    Paul,

    Thanks for reaching out to the E2E forums.

    It looks like with the flash API example we(TI) have placed the PLLCR and the CPU_RATE defines in 2 different files(vs the standard examples.h file).  You will also need to modify the CPU_RATE #define in Flash2803x_API_Config.h in this path: C:\ti\c2000\C2000Ware_3_04_00_00\libraries\flash_api\f2803x\include

    Just out of curiosity, you mention making the clock 20MHz to match your PCB design; do you mean you need to run the F2803x at 20MHz to match up to some external sample rate/trigger?  Or are you supplying a 20MHz clock to the F2802x device? 

    Currently the device would need a 10MHz clock(which is the default of the internal 0 pin oscillator) to get a CPU rate of 20MHz with the selections you have provided for the PLL and DIVSEL.

    Best,

    Matthew

  • 0 in reply to MatthewPate
    Prodigy 20 points

    Thanks Matthew,

    I just spotted this this morning when I came back to it fresh from the weekend.

    On the 20MHz question, I'm using a development kit for writing the code but the destination board design will be clocked from an external 20MHz oscillator so I need to set the internal 10MHx osc & PLL to simulate the 20MHz that it's destined for.

    Paul