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TMS320F280049C: SVPWM examples

David Nyarko
Expert 1625 points

Part Number: TMS320F280049C
Other Parts Discussed in Thread: C2000WARE

Are there any state vector pwm examples/routines for implementation on the F28004x Launchpad..

I have begun using the "epwm_ex2_updown_aq.c"  f28004x epwm driverlib example  in the C2000Ware_3_04_00_00

but wondering how i can have the phase updates of 3 epwms synchronized when they each have separate ISRs . Unless i am 

using a wrong approach.

Thanks

David Nyarko

  • 0
    TI__Mastermind 24095 points

    Hi,


    there are several examples in https://www.ti.com/tool/C2000WARE-MOTORCONTROL-SDK
    on SVPWM and updating 3 phases.
    Please refer to the examples and revert back to us if you still have any issues in understanding or configuration.

  • 0 in reply to Subrahmanya
    Expert 1625 points

    Thanks, i will look into that

  • 0 in reply to Subrahmanya
    Expert 1625 points

    I installed the SDK but do not know which example to follow. 

    I just decided to write my own code based on information in one the TI training modules "Space vector modulation, field Wwakening, d-q axis decoupling and operation of AC induction motors." and the sector selection approach . 

    https://training.ti.com/teaching-old-motors-new-tricks-part-3-space-vector-modulation-field-weakening-d-q-axis-decoupling?context=1137615-31562-31459

    For each reference voltage and angle i calculate T1, T2 and the Null vector times  using the formula  in the slide around the 14 minute mark

    I am using EPWM1, EPWM2 and EPWM3. 

    I have only set up EPWM 1 to generate an Interrupt and i update the Compare registers (EPWM1, EPWM2 and EPWM3) in the EPWM1 ISR. 

    2 questions:

    - I set up all the 3 EPWMs in the UP-DOWN count mode and included the following:

    EPWM_setCounterCompareShadowLoadMode(base, EPWM_COUNTER_COMPARE_A, EPWM_COMP_LOAD_ON_CNTR_ZERO); // Load on zero
    EPWM_setCounterCompareShadowLoadMode(base, EPWM_COUNTER_COMPARE_B, EPWM_COMP_LOAD_ON_CNTR_ZERO); // Load on zero

    - Also my EPWM1 ISR setup has the following:

    EPWM_setInterruptSource(EPWM1_BASE, EPWM_INT_TBCTR_ZERO);
    EPWM_enableInterrupt(EPWM1_BASE);
    EPWM_setInterruptEventCount(EPWM1_BASE, 1U);

    - I complete the initialization of all 3 EPWMs with the following.

        SysCtl_enablePeripheral(SYSCTL_PERIPH_CLK_TBCLKSYNC);

    Questions:

    1)

    If EPWM1 ISR interrupt is entered when the counter is zero, and i compute and load the new CCA and CCB values for all 3 EPWMs,

    a) will they be updated and used within that "period" (i.e before the next EPWM1 counter zero), OR

    b) they will only be updated at the next EPWM1 counter zero ( which is also the next time the ISR is executed) . ie A one period delay for all 3 EPWMs to output their intended waveform patterns.

    2) How can i ensure all the 3 EPWMs will start at the same time . Is it automatic that based on the 

        SysCtl_enablePeripheral(SYSCTL_PERIPH_CLK_TBCLKSYNC);

    function?

    And does it maintain synchronization across all 2 EPWMs as long as the program is execution?

    Thanks

    David

  • +1 in reply to David Nyarko
    TI__Mastermind 24095 points
    David Nyarko said:

    If EPWM1 ISR interrupt is entered when the counter is zero, and i compute and load the new CCA and CCB values for all 3 EPWMs,

    a) will they be updated and used within that "period" (i.e before the next EPWM1 counter zero), OR

    b) they will only be updated at the next EPWM1 counter zero ( which is also the next time the ISR is executed) . ie A one period delay for all 3 EPWMs to output their intended waveform patterns.

    next PWM cycle. so it's b)

    David Nyarko said:

    2) How can i ensure all the 3 EPWMs will start at the same time . Is it automatic that based on the 

        SysCtl_enablePeripheral(SYSCTL_PERIPH_CLK_TBCLKSYNC);

    function?

    And does it maintain synchronization across all 2 EPWMs as long as the program is execution?

    Yes, TBCLKSYNC is used to start all the PWMs at once. They will remain so unless the configuration (TBPRD chage or Synchronization enabled) is changed.