Hi.
I have a question regarding BRS setup.
If the value of "initParams.brsEnable" in line 221 is set to 0, it was confirmed that the communication operation is normal.
However, if the value of" initParams.brsEnable" is set to 1, the sending operation does not work. Please check if there are any wrong settings
//
// Included Files
//
#include "DSK2838x_Define.h"
#include "easy28x_bitfield_v9.4.h"
//
// Defines
//
#define MCAN_STD_ID_FILT_START_ADDR (0x0U)
#define MCAN_STD_ID_FILTER_NUM (32U) //(1U)
#define MCAN_EXT_ID_FILT_START_ADDR (0x14U)
#define MCAN_EXT_ID_FILTER_NUM (1U)
#define MCAN_TX_BUFF_START_ADDR (0x11U)
#define MCAN_TX_BUFF_SIZE (10U)
#define MCAN_FIFO_1_START_ADDR (0xc0U)
#define MCAN_FIFO_1_NUM (10U)
#define MCAN_TX_EVENT_START_ADDR (0x100U)
#define MCAN_TX_EVENT_SIZE (10U)
#define MCAN_EXT_ID_AND_MASK (0x1FFFFFFFU)
#define MCAN_RX_BUFF_START_ADDR (948U)
#define MCAN_FIFO_0_START_ADDR (548U)
#define MCAN_FIFO_0_NUM (5U)
#define MCAN_MSG_INT (0x81200)
//
// Global Variables.
//
volatile uint32_t isrIntr0Flag = 1U;
volatile uint32_t isrIntr1Flag = 1U;
volatile uint16_t monEn = 0x0;
volatile unsigned long msgCount = 0;
volatile unsigned long error = 0;
//
// Function Prototype.
//
static void MCANConfig(void);
static void MCANIntrConfig(void);
__interrupt void MCANIntr0ISR(void);
__interrupt void MCANIntr1ISR(void);
__interrupt void cpu_timer0_isr(void);
int forcnt=0, testcnt=0, txtest=0, testNum=1;
uint32_t txbto_val=0;
MCAN_TxBufElement txMsg;
MCAN_RxBufElement rxMsg;
uint32_t time_250_cnt=0, test_data=0;
MCAN_RxNewDataStatus newData;
void setup_Variables(void);
// Main
void main(void)
{
int i = 0;
volatile uint32_t mode = 0U;
//=============================================================
// Initialize device clock and peripherals
//-------------------------------------------------------------
Device_init();//InitSysCtrl();
//=============================================================
#if F2838xS_CPU1_CM || F2838xD_CPU1_CM || F2838xD_CPU1_CPU2_CM
// CMCLK = 125MHz
// Set up CMCLK to use AUXPLL as the clock source and set the clock divider to 1.
// assumption : AUXPLLCLK is set to 125Mhz in InitSysCtrl();
Device_bootCM(BOOTMODE_BOOT_TO_FLASH_SECTOR0);
#endif
#if F2838xD_CPU1_CPU2 || F2838xD_CPU1_CPU2_CM
// CMCLK = 125MHz
// Set up CMCLK to use AUXPLL as the clock source and set the clock divider to 1.
// assumption : AUXPLLCLK is set to 125Mhz in InitSysCtrl();
Device_bootCPU2(BOOTMODE_BOOT_TO_FLASH_SECTOR0);
#endif
Device_initGPIO();//InitGpio();
#ifdef MCAN
//
// Allocated MCAN shared peripheral to C28x
//
SysCtl_allocateSharedPeripheral(SYSCTL_PALLOCATE_MCAN_A,0x0U);
//
// Setting the MCAN Clock.
//
SysCtl_setMCANClk(SYSCTL_MCANCLK_DIV_5);
//
// Configuring the GPIOs for MCAN.
//
GPIO_setPinConfig(DEVICE_GPIO_CFG_MCANRXA);
GPIO_setPinConfig(DEVICE_GPIO_CFG_MCANTXA);
#endif
//=============================================================
// Disable CPU interrupts
//-------------------------------------------------------------
//DINT;
//=============================================================
//=============================================================
// Initialize the PIE control registers to their default state.
// The default state is all PIE interrupts disabled and flags
// are cleared.
//-------------------------------------------------------------
InitPieCtrl();
//=============================================================
//=============================================================
// Disable CPU interrupts and clear all CPU interrupt flags
//-------------------------------------------------------------
IER = 0x0000;
IFR = 0x0000;
//=============================================================
//=============================================================
// Initialize the PIE vector table with pointers to the shell Interrupt
// Service Routines (ISR)
//-------------------------------------------------------------
InitPieVectTable();
//-------------------------------------------------------------
// Map ISR functions
EALLOW;
PieVectTable.TIMER0_INT = &cpu_timer0_isr;
EDIS;
//Interrupt_register(INT_EQEP1, &eqepISR);
//=============================================================
#ifdef EASYDSP
#if F2837xD_CPU1_CPU2 || F2838xS_CPU1_CM || F2838xD_CPU1_CM || F2838xD_CPU1_CPU2 || F2838xD_CPU1_CPU2_CM
easyDSP_Boot_Sync();
#endif
easyDSP_SCI_Init();
#endif
//=============================================================
// Initialize the Device Peripheral. For this example, only initialize the
// Cpu Timers.
//-------------------------------------------------------------
InitCpuTimers();
//-------------------------------------------------------------
// Configure CPU-Timer 0, 1, and 2 to interrupt every second:
// 200MHz CPU Freq, 1 second Period (in uSeconds)
//-------------------------------------------------------------
ConfigCpuTimer(&CpuTimer0, 200, 250);
//-------------------------------------------------------------
// To ensure precise timing, use write-only instructions to write to the
// entire register. Therefore, if any of the configuration bits are changed
// in ConfigCpuTimer and InitCpuTimers, the below settings must also be
// be updated.
//-------------------------------------------------------------
CpuTimer0Regs.TCR.all = 0x4000;
//=============================================================
//=============================================================
// Enable CPU int1 which is connected to CPU-Timer 0
//-------------------------------------------------------------
IER |= M_INT1;
//-------------------------------------------------------------
// Enable TINT0 in the PIE: Group 1 interrupt 7
//-------------------------------------------------------------
PieCtrlRegs.PIEIER1.bit.INTx7 = 1;
//=============================================================
Interrupt_enable(INT_TIMER0);
//
// Initialize message to transmit.
//
txMsg.id = ((uint32_t)(0x11)); // Identifier Value.
txMsg.rtr = 0U; // Transmit data frame.
txMsg.xtd = 1U; // extended identifier
txMsg.esi = 0U; // ESI bit in CAN FD format depends only on error
// passive flag.
txMsg.dlc = 8U; // CAN FD: transmit frame has 12/16/20/24/32/48/64 data bytes
txMsg.brs = 1U; // CAN FD frames transmitted with bit rate
// switching.
txMsg.fdf = 1U; // Frame transmitted in CAN FD format.
txMsg.efc = 1U; // Store Tx events.
txMsg.mm = 0xAAU; // Message Marker.
//
// Data bytes.
//
for(i=0;i<64;i++)
{
txMsg.data[i] = i;
}
//
// Configure MCAN.
//
MCANConfig();
for(;;)
{
}
}
//
// This function will configure MCAN module.
//
static void MCANConfig(void)
{
MCAN_RevisionId revId;
MCAN_InitParams initParams;
MCAN_ConfigParams configParams;
MCAN_MsgRAMConfigParams msgRAMConfigParams;
MCAN_StdMsgIDFilterElement stdFiltelem;
MCAN_ExtMsgIDFilterElement extFiltelem;
MCAN_BitTimingParams bitTimes;
//
// Initialize MCAN Init parameters.
//
initParams.fdMode = 0x1U; // FD operation enabled.
initParams.brsEnable = 0x0U; // Bit rate switching for
// transmissions enabled.
initParams.txpEnable = 0x1U; // Transmit pause disabled.
initParams.efbi = 0x0U; // Edge filtering disabled.
initParams.pxhddisable = 0x0U; // Protocol exception handling enabled.
initParams.darEnable = 0x1U; // Automatic retransmission of messages
// not transmitted successfully enabled.
initParams.wkupReqEnable = 0x1U; // Wakeup request is enabled.
initParams.autoWkupEnable = 0x1U; // Auto-Wakeup is enabled.
initParams.emulationEnable = 0x1U; // Emulation/Debug Suspend is enabled.
initParams.tdcEnable = 0x1U; // Transmitter Delay Compensation is
// enabled.
initParams.wdcPreload = 0xFFU; // Start value of the Message RAM
// Watchdog Counter preload.
//
// Transmitter Delay Compensation parameters.
//
initParams.tdcConfig.tdcf = 0xAU;
initParams.tdcConfig.tdco = 0x6U;
//
// Initialize MCAN Config parameters.
//
configParams.monEnable = 0; // Bus Monitoring Mode is disabled.
configParams.asmEnable = 0x0U; // Normal CAN operation.
configParams.tsPrescalar = 0x2U; // Prescaler Value.
configParams.tsSelect = 0x2U; // Timestamp counter value.
configParams.timeoutSelect = MCAN_TIMEOUT_SELECT_CONT;
// Time-out counter source select.
configParams.timeoutPreload = 0xFFFFU; // Start value of the Timeout
// Counter.
configParams.timeoutCntEnable = 0x0U; // Time-out Counter is disabled.
configParams.filterConfig.rrfs = 0x1U; // Reject all remote frames with
// 29-bit extended IDs.
configParams.filterConfig.rrfe = 0x1U; // Reject all remote frames with
// 11-bit standard IDs.
configParams.filterConfig.anfe = 0x1U; // Accept in Rx FIFO 1.
configParams.filterConfig.anfs = 0x1U; // Accept in Rx FIFO 1.
//
// Initialize Message RAM Sections Configuration Parameters.
//
msgRAMConfigParams.flssa = MCAN_STD_ID_FILT_START_ADDR;
// Standard ID Filter List Start Address.
msgRAMConfigParams.lss = MCAN_STD_ID_FILTER_NUM;
// List Size: Standard ID.
msgRAMConfigParams.flesa = MCAN_EXT_ID_FILT_START_ADDR;
// Extended ID Filter List Start Address.
msgRAMConfigParams.lse = MCAN_EXT_ID_FILTER_NUM;
// List Size: Extended ID.
msgRAMConfigParams.txStartAddr = MCAN_TX_BUFF_START_ADDR;
// Tx Buffers Start Address.
msgRAMConfigParams.txBufNum = MCAN_TX_BUFF_SIZE;
// Number of Dedicated Transmit Buffers.
msgRAMConfigParams.txFIFOSize = MCAN_TX_BUFF_SIZE; // No Tx FIFO/Queue.
msgRAMConfigParams.txBufMode = 0U; //Tx FIFO operation
msgRAMConfigParams.txBufElemSize = MCAN_ELEM_SIZE_64BYTES;
// Tx Buffer Element Size.
msgRAMConfigParams.txEventFIFOStartAddr = MCAN_TX_EVENT_START_ADDR;
// Tx Event FIFO Start Address.
msgRAMConfigParams.txEventFIFOSize = MCAN_TX_BUFF_SIZE;
// Event FIFO Size.
msgRAMConfigParams.txEventFIFOWaterMark = 3U;
// Level for Tx Event FIFO watermark interrupt.
msgRAMConfigParams.rxFIFO0startAddr = MCAN_FIFO_0_START_ADDR;
// Rx FIFO0 Start Address.
msgRAMConfigParams.rxFIFO0size = MCAN_FIFO_0_NUM;
// Number of Rx FIFO elements.
msgRAMConfigParams.rxFIFO0waterMark = 3U; // Rx FIFO0 Watermark.
msgRAMConfigParams.rxFIFO0OpMode = 0U; // FIFO blocking mode.
msgRAMConfigParams.rxFIFO1startAddr = MCAN_FIFO_1_START_ADDR;
// Rx FIFO1 Start Address.
msgRAMConfigParams.rxFIFO1size = MCAN_FIFO_1_NUM;
// Number of Rx FIFO elements.
msgRAMConfigParams.rxFIFO1waterMark = 3U; // Level for Rx FIFO 1
// watermark interrupt.
msgRAMConfigParams.rxFIFO1OpMode = 0U; // FIFO blocking mode.
msgRAMConfigParams.rxBufStartAddr = MCAN_RX_BUFF_START_ADDR;
// Rx Buffer Start Address.
msgRAMConfigParams.rxBufElemSize = MCAN_ELEM_SIZE_64BYTES;
// Rx Buffer Element Size.
msgRAMConfigParams.rxFIFO0ElemSize = MCAN_ELEM_SIZE_64BYTES;
// Rx FIFO0 Element Size.
msgRAMConfigParams.rxFIFO1ElemSize = MCAN_ELEM_SIZE_64BYTES;
// Rx FIFO1 Element Size.
//
// Initialize Tx Buffer Configuration parameters.
//
stdFiltelem.sfid2 = 0x0U; // Standard Filter ID 2.
stdFiltelem.sfid1 = 0x1U; // Standard Filter ID 1.
stdFiltelem.sfec = 0x7U; // Store into Rx Buffer or as
// debug message, configuration of SFT[1:0] ignored.
stdFiltelem.sft = 0x0U; // Range filter from SFID1 to SFID2.
//
// Initialize Tx Buffer Configuration parameters.
//
extFiltelem.efid2 = (0x9U << 16U);
extFiltelem.efid2 |= 0xFFU;
extFiltelem.efid1 = (0x0U << 16U);
extFiltelem.efid1 |= 0xFFU;
extFiltelem.efec = 0x6U;
extFiltelem.eft = 0x0U;
//
// Initialize bit timings.
//
// Nominal = 1M / Data = 2M
bitTimes.nomRatePrescalar = 0x4U; // Nominal Baud Rate Pre-scaler.
bitTimes.nomTimeSeg1 = 0x4U; // Nominal Time segment before sample point.
bitTimes.nomTimeSeg2 = 0x1U; // Nominal Time segment after sample point.
bitTimes.nomSynchJumpWidth = 0x0U; // Nominal (Re)Synchronization Jump Width Range.
bitTimes.dataRatePrescalar = 0x0U; // Data Baud Rate Pre-scaler.
bitTimes.dataTimeSeg1 = 0x6U; // Data Time segment before sample point.
bitTimes.dataTimeSeg2 = 0x1U; // Data Time segment after sample point.
bitTimes.dataSynchJumpWidth = 0x0U; // Data (Re)Synchronization Jump Width.
//
// Get MCANSS Revision ID.
//
MCAN_getRevisionId(MCAN0_BASE, &revId);
//
// Wait for Memory initialization to be completed.
//
while(FALSE == MCAN_isMemInitDone(MCAN0_BASE));
//
// Put MCAN in SW initialization mode.
//
MCAN_setOpMode(MCAN0_BASE, MCAN_OPERATION_MODE_SW_INIT);
//
// Wait till MCAN is not initialized.
//
while (MCAN_OPERATION_MODE_SW_INIT != MCAN_getOpMode(MCAN0_BASE));
//
// Initialize MCAN module.
//
MCAN_init(MCAN0_BASE, &initParams);
//
// Configure MCAN module.
//
MCAN_config(MCAN0_BASE, &configParams);
//
// Configure Bit timings.
//
MCAN_setBitTime(MCAN0_BASE, &bitTimes);
//
// Set Extended ID Mask.
//
MCAN_setExtIDAndMask(MCAN0_BASE, MCAN_EXT_ID_AND_MASK);
//
// Configure Message RAM Sections
//
MCAN_msgRAMConfig(MCAN0_BASE, &msgRAMConfigParams);
//
// Configure Standard ID filter element
//
MCAN_addStdMsgIDFilter(MCAN0_BASE, 0U, &stdFiltelem);
//
// Configure Extended ID filter element
//
MCAN_addExtMsgIDFilter(MCAN0_BASE, 0U, &extFiltelem);
//
// Enable internal loopback mode
//
//MCAN_lpbkModeEnable(MCAN0_BASE, MCAN_LPBK_MODE_EXTERNAL, TRUE);
//
// Take MCAN out of the SW initialization mode
//
MCAN_setOpMode(MCAN0_BASE, MCAN_OPERATION_MODE_NORMAL);
while (MCAN_OPERATION_MODE_NORMAL != MCAN_getOpMode(MCAN0_BASE));
}
// cpuTimer0ISR - CPU Timer0 ISR with interrupt counter
//int can_fd_test=0, can_fd_flag=0, can_tx_id=0x11, set_250_cnt=2;
__interrupt void cpu_timer0_isr(void)
{
CpuTimer0.InterruptCount++;
/*if(time_250_cnt++>=set_250_cnt)
{
time_250_cnt=0;
if(can_fd_test==1)
{
txMsg.id = ((uint32_t)(can_tx_id));
if(can_tx_id++>=0x13) can_tx_id=0x11;
txMsg.data[0] = test_data++;
if(test_data>=100) test_data=0;
MCAN_writeMsgRam(MCAN0_BASE, MCAN_MEM_TYPE_BUF, 1U, &txMsg);
MCAN_txBufAddReq(MCAN0_BASE,1U);
}
}*/
MCAN_writeMsgRam(MCAN0_BASE, MCAN_MEM_TYPE_BUF, 1U, &txMsg);
MCAN_txBufAddReq(MCAN0_BASE,1U);
//
// Read Message RAM.
//
MCAN_readMsgRam(MCAN0_BASE, MCAN_MEM_TYPE_FIFO, 0U, MCAN_RX_FIFO_NUM_1,
&rxMsg);
MCAN_writeRxFIFOAck(MCAN0_BASE, MCAN_RX_FIFO_NUM_1, 0);
// Acknowledge this interrupt to receive more interrupts from group 1
PieCtrlRegs.PIEACK.all = PIEACK_GROUP1;
}
Please help. Thank you
