Other Parts Discussed in Thread: C2000WARE,
Dears:
I use GPIO9 as LINTXA, write TDO register, but there are no date out from TX pin. the Header transmit is OK, but the date is not OK, always high level.
attachment is my part of code and LIN Initialization code.
static void Init_LINSCI(void)
{
EALLOW;
//====================================================================
/*
SCIGCR0 --- Address
*/
// LinaRegs.SCIGCR0.all = 0;
//Reset module and release reset.
LinaRegs.SCIGCR0.bit.RESET = 0;
LinaRegs.SCIGCR0.bit.RESET = 1;
//LIN into software reset mode
LinaRegs.SCIGCR1.bit.SWnRST = 0;
//Select LIN Mode
LinaRegs.SCIGCR1.bit.LINMODE = 1; // lin mode enable.
//Configure LIN mode
LinaRegs.SCIGCR1.bit.CLK_MASTER = 1; // 1-->Master, 0-->Slave
// LinaRegs.SCIGCR1.bit.TIMINGMODE = 1; // Must be set to 1 when module is configured for SCI operation
LinaRegs.SCIGCR1.bit.ADAPT = 0; // Fixed baud rate
LinaRegs.SCIGCR1.bit.COMMMODE= 0; // ID bits 4 and 5 not used for length control
LinaRegs.SCIGCR1.bit.CONT = 1; // Continue on Emulation suspend
LinaRegs.SCIGCR1.bit.CTYPE = 0; // LIN 2.0 Enhanced checksum used
LinaRegs.SCIGCR1.bit.HGENCTRL = 1; // ID match vs LinaRegs.bit.IDSLAVETASKBYTE
LinaRegs.SCIGCR1.bit.LOOPBACK = 0; // External communication mode
LinaRegs.SCIGCR1.bit.MBUFMODE = 1; // Buffered mode
LinaRegs.SCIGCR1.bit.PARITYENA = 0; // Check received ID for parity
LinaRegs.SCIGCR1.bit.RXENA = 1; // Enable RX pin
LinaRegs.SCIGCR1.bit.TXENA = 1; // Enable TX pin
//More LIN configs
// LinaRegs.SCIGCR2.bit.CC = 1; // Validate checksum
//Set all interrupts to disabled
LinaRegs.SCICLEARINT.all = 0xFFFFFFFF;
// LinaRegs.SCISETINT.bit.SETRXINT = 1; // Receiver Interrupt is enabled.
// LinaRegs.SCISETINT.bit.SETTXINT = 1; // Transmitter Interrupt is enabled.
// LinaRegs.SCICLEARINT.bit.CLRTXINT = 1; // Transmitter Interrupt is disabled.
// LinaRegs.SCISETINT.bit.SETBRKDTINT = 1; // break-detect interrupt is enabled.
// LinaRegs.SCISETINT.bit.SETIDINT = 1; // Set Identification interrupt.
// LinaRegs.SCISETINT.bit.SETISFEINT = 1; // Set inconsistent-sync-field-error interrupt.
//
LinaRegs.SCICLEARINTLVL.bit.CLRRXINTLVL = 1; // Receiver Interrupt level mapped to INT0 line.
// LinaRegs.SCICLEARINTLVL.bit.CLRBRKDTINTLVL = 1; // Break-detect Interrupt level mapped to INT0 line.
LinaRegs.SCICLEARINTLVL.bit.CLRIDINTLVL = 1; // id Interrupt level mapped to INT0 line.
LinaRegs.SCICLEARINTLVL.bit.CLRISFEINTLVL = 1; // Inconsistent-Sync-Field-Error interrupt level mapped to INT0 line.
LinaRegs.SCISETINTLVL.bit.SETTXINTLVL = 1; // Transmitter Interrupt level mapped to INT1 line.
//Baud Rate Settings - 60MHz device
LinaRegs.BRSR.bit.SCI_LIN_PSH = 0;
LinaRegs.BRSR.bit.SCI_LIN_PSL = 389; // 4.8 kbps
LinaRegs.BRSR.bit.M = 10;
// LinaRegs.BRSR.bit.SCI_LIN_PSH = 0;
// LinaRegs.BRSR.bit.SCI_LIN_PSL = 194; // 9.6 kbps
// LinaRegs.BRSR.bit.M = 5;
// LinaRegs.MBRSR = 92; //20kHz (max autobaud rate)
//LIN Character Size and Length
LinaRegs.SCIFORMAT.bit.LENGTH = 7; // 8 bit transmission/response
// LinaRegs.SCIFORMAT.bit.CHAR = 7; // The character is 8 bits long.
// LinaRegs.SCIFORMAT.all = 0x00070007;
//SYNC Field Configuration
LinaRegs.LINCOMP.bit.SBREAK = 0; // Sync break is 13 + 5 = 18 Tbits
LinaRegs.LINCOMP.bit.SDEL = 0; // Sync delimiter is 1 + 3 = 4 Tbits
//LIN MASK Configuartion
LinaRegs.LINMASK.bit.TXIDMASK = 0x0a;//0xFF; // Mask ID so TX match will always happen
LinaRegs.LINMASK.bit.RXIDMASK = 0x0a;//0xFF; // Mask ID so RX match will always happen
//IODFT Configuarations
// LinaRegs.IODFTCTRL.bit.IODFTENA = 0x0; // IODFT testing module disabled
// LinaRegs.IODFTCTRL.bit.LPBENA = 0; // IODFT loopback disabled
//
LinaRegs.LINID.bit.IDSLAVETASKBYTE = 0x30; // 0x30
//Release SCI from software reset state - End of Config
LinaRegs.SCIGCR1.bit.SWnRST = 1;
EDIS;
}
