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Hi Mohammand,
I have reached out to the Simulink experts, please give a few days for them to revert back.
Thanks,
Ashwini
Hi Ashwini,
Thanks for the response. I want to attach the code here. How can I do this?
Regards,
Mohammad
Hi Mohammad,
Can you also please attach the sample model where you are seeing this issue?
Regards,
Ram Alla.
2627.TI_CLA_TAPAS_PLL_code_gen_2018b_iq_cla_18b.zipHi Ram,
I have attached the file here. I have updated the counter cut value. Please follow the updated file. Thank you!
Regards,
Mohammad
Hi Mohammad,
I don't see any issue with the Simulink model. However, as you mentioned that the ADC measurement of three phase output voltage is not correct I suspect that the configured value of 7 for 'SOCx acquisition window' parameter may not be sufficient to read the input voltage of both channels A and B. There could be a chance that up to 7 cycles, the Sampling and Hold duration for channel B could be overlapping with the conversion phase of the previous conversion of channel A which may result in incorrect value. Updating the 'SOCx acquisition window' parameter value to 16 might help in this case.
In case this does not resolve the issue, it would be best for you to get in touch with our support channel as we need to understand this issue in depth and debug further. When we have a support ticket, our internal process enables us to involve right people on this issue and we will immediately get in touch with you to understand the case in more detailed way.
Please connect to us at:
www.mathworks.com/support.html
Best Regards,
Ram Alla | MathWorks
Hi Ram,
Thanks for the reply. I have followed your instructions. Unfortunately, it does not solve the issue. I am planning to seek support from MathWorks. Thank you!
Regards,
Mohammad
Mohammad,
I will close the thread from here as you are working with MathWorks team directly on their forum.