I am attempting to use the EMIF to access registers within an FPGA.
I configured everything to run on EMIF2 CS2 in 16-bit Async mode. The registers within the FPGA are only 16bit so I don't want to operate with 32-bit accesses as it would be unnecessary overhead ( 1 extra transaction per access).
The Design and Usage Guide section 5.1 and table 7 seem to imply the EMIF can operate with just 16-bit access, but I have not found out how to do so yet.
App note section 5.1: "The CPU, DMA, and CLA are each capable of using 16-bit and 32-bit access modes for data operations."

I used emif1_16bit_asram.c as an example on how to get everything working and I can see data coming though and being written into the FPGA registers using signal tap so I know the interface is functional. When writing or reading in the code I am also using 16 unsigned int data types.
I'm pretty confused at this point what section 5.1 is trying to say with the 16-bit and 32-bit access modes in context of table 7.
Is it possible to run only a single 16-bit transaction per access request?
Thanks for your help,
Max
 
				 
		 
					 
                           
				