Hi,
my customer is using 100pin F280049, and A10, B1, C10 share one pin on F280049.
They applied one specific voltage on this pin, and A10, B1 can sample correctly. But C10 sampling result register is always 0.
The same problem happens on all ADCC channels.
The configuration is as below: all channels are started by EPWM2 SOCA.
Could you please help take a look what's wrong here?
#include "DRIVER\Driver.h"
INT16S wGridVolt_Bias = 0;
INT16S wOpCurr_Bias = 0;
INT16S wInvVolt_Bias = 0;
INT16S wInvCurr_Bias = 0;
INT16S wBusVolt_Bias = 0;
INT16S wLowLoadCurr_Bias = 0;
INT16S wBusCurr_Bias = 0;
INT16S wLlcI_Bias = 0;
INT16S wBatVolt_Bias = 0;
INT16S wTxtTemp_Bias = 0;
INT16S wBatTemp_Bias = 0;
INT16S wInvTemp_Bias = 0;
void InitEPWM(void);
void InitECAP(void);
void InitADC(void);
void InitSCI(void);
void InitCAN(void);
void InitPieINT(void);
void InitGPIO(void);
void sADCali(void);
void InitDsp(void)
{
//Step 1. Initialize System Control:
//PLL, WatchDog,enabe Peripheral Clocks
//This example function is found in the f28004x_sysctrl.c file.
InitSysCtrl();
//Step 2. Initialize GPIO
InitGpio();
//Step 3. Clear all __interrupts and initialize PIE vector table:
//Disable CPU __interrupts
DINT;
//Initialize the PIE control registers to their default state.
//The default state is all PIE interrupts disabled and flags
//are cleared.
InitPieCtrl();
//Disable CPU interrupts and clear all CPU interrupt flags:
IER = 0x0000;
IFR = 0x0000;
//Initialize the PIE vector table with pointers to the shell Interrupt
//Service Routines (ISR).
InitPieVectTable();
InitGPIO();
InitEPWM();
InitECAP();
InitADC();
InitSCI();
// InitCAN();
EALLOW; // This is needed to write to EALLOW protected registers
PieVectTable.TIMER2_INT = &Int_OSTimeBase;
PieVectTable.EPWM1_INT = &Int_Pfc;
PieVectTable.EPWM2_INT = &Int_Inv;
PieVectTable.ECAP1_INT = &Int_GridZeroCross;
PieVectTable.ECAP2_INT = &Int_InvZeroCross;
PieVectTable.ECAP3_INT = &Int_SynZeroCross;
PieVectTable.SCIA_RX_INT = &Int_SciARx;
PieVectTable.SCIA_TX_INT = &Int_SciATx;
PieVectTable.SCIB_RX_INT = &Int_SciBRx;
PieVectTable.SCIB_TX_INT = &Int_SciBTx;
//PieVectTable.CANB1_INT = &Int_Can0;
//PieVectTable.CANA1_INT = &Int_Can1;
PieVectTable.USER12_INT = &OSCtxSw; //trap #31
EDIS; // This is needed to disable write to EALLOW protected registers
InitCpuTimers();
StartCpuTimer2();
DINT;
IER = 0x0000;
IFR = 0x0000;
InitPieINT();
IER |=( M_INT3 | M_INT4 | M_INT9 |M_INT14);
sADCali();
EINT;
}
void InitGPIO(void)
{
EALLOW;
// Enable PWM1-8 on GPIO0-GPIO15
GpioCtrlRegs.GPAPUD.bit.GPIO0 = 0; // Enable pullup on GPIO0
GpioCtrlRegs.GPAPUD.bit.GPIO1 = 0; // Enable pullup on GPIO1
GpioCtrlRegs.GPAPUD.bit.GPIO2 = 0; // Enable pullup on GPIO2
GpioCtrlRegs.GPAPUD.bit.GPIO3 = 0; // Enable pullup on GPIO3
GpioCtrlRegs.GPAPUD.bit.GPIO4 = 0; // Enable pullup on GPIO4
GpioCtrlRegs.GPAPUD.bit.GPIO5 = 0; // Enable pullup on GPIO5
GpioCtrlRegs.GPAPUD.bit.GPIO6 = 0; // Enable pullup on GPIO6
GpioCtrlRegs.GPAPUD.bit.GPIO7 = 0; // Enable pullup on GPIO7
GpioCtrlRegs.GPAPUD.bit.GPIO8 = 0; // Enable pullup on GPIO8
GpioCtrlRegs.GPAPUD.bit.GPIO9 = 0; // Enable pullup on GPIO9
GpioCtrlRegs.GPAPUD.bit.GPIO10 = 0; // Enable pullup on GPIO10
GpioCtrlRegs.GPAPUD.bit.GPIO11 = 0; // disable pullup on GPIO11
GpioCtrlRegs.GPAPUD.bit.GPIO12 = 0; // disable pullup on GPIO12
GpioCtrlRegs.GPAPUD.bit.GPIO13 = 0; // disable pullup on GPIO13
GpioCtrlRegs.GPAPUD.bit.GPIO14 = 0; // disable pullup on GPIO14
GpioCtrlRegs.GPAPUD.bit.GPIO15 = 0; // disable pullup on GPIO15
GpioCtrlRegs.GPAMUX1.bit.GPIO0 = 1; // GPIO0 = PWM1A INVPWM_NU
GpioCtrlRegs.GPAMUX1.bit.GPIO1 = 1; // GPIO1 = PWM1B INVPWM_ND
GpioCtrlRegs.GPAMUX1.bit.GPIO2 = 1; // GPIO2 = PWM2A INVPWM_LU
GpioCtrlRegs.GPAMUX1.bit.GPIO3 = 1; // GPIO3 = PWM2B INVPWM_LD
GpioCtrlRegs.GPAMUX1.bit.GPIO4 = 1; // GPIO4 = PWM3A DISCHG_1U
GpioCtrlRegs.GPAMUX1.bit.GPIO5 = 1; // GPIO5 = PWM3B DISCHG_1D
GpioCtrlRegs.GPAMUX1.bit.GPIO6 = 1; // GPIO6 = PWM4A DISCHG_2U
GpioCtrlRegs.GPAMUX1.bit.GPIO7 = 1; // GPIO7 = PWM4B DISCHG_2D
GpioCtrlRegs.GPAMUX1.bit.GPIO8 = 1; // GPIO8 = PWM5A CHG_PWM_U
GpioCtrlRegs.GPAMUX1.bit.GPIO9 = 1; // GPIO9 = PWM5B CHG_PWM_D
GpioCtrlRegs.GPAMUX1.bit.GPIO10 = 1; // GPIO10 = PWM6A SFT.RLY.L
GpioCtrlRegs.GPAMUX1.bit.GPIO11 = 1; // GPIO11 = PWM6B Fan.Speed
GpioCtrlRegs.GPAMUX1.bit.GPIO12 = 1; // GPIO12 = PWM7A OP.RLY
GpioCtrlRegs.GPAMUX1.bit.GPIO13 = 0; // GPIO13 = IO LLCI.OCP
GpioCtrlRegs.GPAMUX1.bit.GPIO14 = 1; // GPIO14 = PWM8A PWM_BUCK
GpioCtrlRegs.GPAMUX1.bit.GPIO15 = 0; // GPIO15 = IO SPS.SD
// InputXbarRegs.INPUT3SELECT = 13;//ʹ��INPUT3--GPIO13����LLCI.OCP
// GpioCtrlRegs.GPADIR.bit.GPIO13 = 0; //��������
// GpioCtrlRegs.GPAPUD.bit.GPIO13 = 0; //��������
// GpioCtrlRegs.GPAQSEL1.bit.GPIO13 = 3; //GPIO����Ϊ��ͬ��ģʽ
GpioCtrlRegs.GPAPUD.bit.GPIO15 = 1; // disable pullup on GPIO15 SPS-SD
GpioDataRegs.GPACLEAR.bit.GPIO15 = 1; // Load output latch to low
GpioCtrlRegs.GPAMUX1.bit.GPIO15 = 0; // GPIO15 = I/O
GpioCtrlRegs.GPADIR.bit.GPIO15 = 1; // GPIO15 = output
GpioCtrlRegs.GPAPUD.bit.GPIO16 = 0; // Enable pullup on GPIO16 AC.ON.LED
GpioDataRegs.GPACLEAR.bit.GPIO16 = 1; // Load output latch to low
GpioCtrlRegs.GPAMUX2.bit.GPIO16 = 0; // GPIO16 = I/O
GpioCtrlRegs.GPADIR.bit.GPIO16 = 1; // GPIO16 = output
GpioCtrlRegs.GPAPUD.bit.GPIO17 = 1; // Enable pullup on GPIO17 AC.ON/OFF
GpioDataRegs.GPACLEAR.bit.GPIO17 = 1; // Load output latch to low
GpioCtrlRegs.GPAMUX2.bit.GPIO17 = 0; // GPIO17 = I/O
GpioCtrlRegs.GPADIR.bit.GPIO17 = 0; // GPIO17 = input
GpioCtrlRegs.GPAPUD.bit.GPIO22 = 0; // Enable pullup on GPIO22 LED_B
GpioDataRegs.GPACLEAR.bit.GPIO22 = 1; // Load output latch to low
GpioCtrlRegs.GPAMUX2.bit.GPIO22 = 0; // GPIO22 = I/O
GpioCtrlRegs.GPADIR.bit.GPIO22 = 1; // GPIO22 = output
GpioCtrlRegs.GPAPUD.bit.GPIO23 = 0; // Enable pullup on GPIO23 LED_A(WP)
GpioDataRegs.GPACLEAR.bit.GPIO23 = 1; // Load output latch to low
GpioCtrlRegs.GPAMUX2.bit.GPIO23 = 0; // GPIO23 = I/O
GpioCtrlRegs.GPADIR.bit.GPIO23 = 1; // GPIO23 = output
// InputXbarRegs.INPUT1SELECT = 25; //ʹ��INPUT1--GPIO25����GRID.V.ZERO
// GpioCtrlRegs.GPADIR.bit.GPIO25 = 0; //��������
// GpioCtrlRegs.GPAPUD.bit.GPIO25 = 0; //��������
// GpioCtrlRegs.GPAQSEL2.bit.GPIO25 = 3; //GPIO����Ϊ��ͬ��ģʽ
//
// InputXbarRegs.INPUT2SELECT = 25; //ʹ��INPUT2--GPIO25����INV.V.ZERO
// GpioCtrlRegs.GPADIR.bit.GPIO25 = 0; //��������
// GpioCtrlRegs.GPAPUD.bit.GPIO25 = 0; //��������
// GpioCtrlRegs.GPAQSEL2.bit.GPIO25 = 3; //GPIO����Ϊ��ͬ��ģʽ
//
// GpioCtrlRegs.GPAPUD.bit.GPIO26 = 0; // Enable pullup on GPIO26
// GpioDataRegs.GPACLEAR.bit.GPIO26 = 1; // Load output latch to low
// GpioCtrlRegs.GPAMUX2.bit.GPIO26 = 0; // GPIO26 = I/O
// GpioCtrlRegs.GPADIR.bit.GPIO26 = 1; // GPIO26 = output
//
// GpioCtrlRegs.GPAPUD.bit.GPIO27 = 0; // Enable pullup on GPIO27
// GpioDataRegs.GPACLEAR.bit.GPIO27 = 1; // Load output latch to low
// GpioCtrlRegs.GPAMUX2.bit.GPIO27 = 0; // GPIO27 = I/O
// GpioCtrlRegs.GPADIR.bit.GPIO27 = 1; // GPIO27 = output
// GpioCtrlRegs.GPAPUD.bit.GPIO28 = 0; // Enable pullup on GPIO28
// GpioDataRegs.GPACLEAR.bit.GPIO28 = 1; // Load output latch to low
// GpioCtrlRegs.GPAMUX2.bit.GPIO28 = 0; // GPIO28 = I/O
// GpioCtrlRegs.GPADIR.bit.GPIO28 = 1; // GPIO28 = output
//
// GpioCtrlRegs.GPAPUD.bit.GPIO29 = 0; // Enable pullup on GPIO29 AC.LED
// GpioDataRegs.GPACLEAR.bit.GPIO29 = 1; // Load output latch to low
// GpioCtrlRegs.GPAMUX2.bit.GPIO29 = 0; // GPIO29 = I/O
// GpioCtrlRegs.GPADIR.bit.GPIO29 = 1; // GPIO29 = output
GpioCtrlRegs.GPAPUD.bit.GPIO30 = 1; // Enable pullup on GPIO30 FAN1.CLOCK
GpioDataRegs.GPACLEAR.bit.GPIO30 = 1; // Load output latch to low
GpioCtrlRegs.GPAMUX2.bit.GPIO30 = 0; // GPIO30 = I/O
GpioCtrlRegs.GPADIR.bit.GPIO30 = 0; // GPIO30 = input
GpioCtrlRegs.GPAPUD.bit.GPIO31 = 1; // Enable pullup on GPIO31 FAN2.CLOCK
GpioDataRegs.GPACLEAR.bit.GPIO31 = 1; // Load output latch to low
GpioCtrlRegs.GPAMUX2.bit.GPIO31 = 0; // GPIO31 = I/O
GpioCtrlRegs.GPADIR.bit.GPIO31 = 0; // GPIO31 = input
//SCIA
GpioCtrlRegs.GPAPUD.bit.GPIO28 = 0; // Enable pullup on GPIO28
GpioCtrlRegs.GPAQSEL2.bit.GPIO28 = 3; // Asynch input
GpioCtrlRegs.GPAMUX2.bit.GPIO28= 1; // GPIO28 = SCIRXDA
GpioCtrlRegs.GPAGMUX2.bit.GPIO28= 0;
GpioCtrlRegs.GPAPUD.bit.GPIO29 = 0; // Enable pullup on GPIO29
GpioCtrlRegs.GPAMUX2.bit.GPIO29 = 1; // GPIO29 = SCITXDA
GpioCtrlRegs.GPAGMUX2.bit.GPIO29 = 0;
//SCIB
GpioCtrlRegs.GPBPUD.bit.GPIO56 = 0; // Enable pullup on GPIO56
GpioCtrlRegs.GPBQSEL2.bit.GPIO56 = 3; // Asynch input
GpioCtrlRegs.GPBMUX2.bit.GPIO56= 2; // GPIO56 = SCIRXDB
GpioCtrlRegs.GPBGMUX2.bit.GPIO56= 1;
GpioCtrlRegs.GPBPUD.bit.GPIO57 = 0; // Enable pullup on GPIO57
GpioCtrlRegs.GPBMUX2.bit.GPIO57 = 2; // GPIO57 = SCITXDB
GpioCtrlRegs.GPBGMUX2.bit.GPIO57 = 1;
GpioCtrlRegs.GPBPUD.bit.GPIO32 = 0; // Enable pullup on GPIO32 SDA
GpioDataRegs.GPBCLEAR.bit.GPIO32 = 1; // Load output latch to low
GpioCtrlRegs.GPBMUX1.bit.GPIO32 = 0; // GPIO32 = I/O
GpioCtrlRegs.GPBDIR.bit.GPIO32 = 1; // GPIO32 = output
GpioCtrlRegs.GPBPUD.bit.GPIO33 = 0; // Enable pullup on GPIO33 SCL
GpioDataRegs.GPBCLEAR.bit.GPIO33 = 1; // Load output latch to low
GpioCtrlRegs.GPBMUX1.bit.GPIO33 = 0; // GPIO33 = I/O
GpioCtrlRegs.GPBDIR.bit.GPIO33 = 1; // GPIO33 = output
GpioCtrlRegs.GPBPUD.bit.GPIO34 = 0; // Enable pullup on GPIO34
GpioDataRegs.GPBSET.bit.GPIO34 = 1;// Load output latch to high
GpioCtrlRegs.GPBMUX1.bit.GPIO34 = 0; // GPIO34 = I/O
GpioCtrlRegs.GPBDIR.bit.GPIO34 = 1; // GPIO34 = output
GpioCtrlRegs.GPBPUD.bit.GPIO35 = 0; // Enable pullup on GPIO35
GpioDataRegs.GPBSET.bit.GPIO35 = 1;// Load output latch to high
GpioCtrlRegs.GPBMUX1.bit.GPIO35 = 0; // GPIO35 = I/O
GpioCtrlRegs.GPBDIR.bit.GPIO35 = 1; // GPIO35 = output
GpioCtrlRegs.GPBPUD.bit.GPIO37 = 0; // Enable pullup on GPIO37
GpioDataRegs.GPBSET.bit.GPIO37 = 1;// Load output latch to high
GpioCtrlRegs.GPBMUX1.bit.GPIO37 = 0; // GPIO37 = I/O
GpioCtrlRegs.GPBDIR.bit.GPIO37 = 1; // GPIO37 = output
GpioCtrlRegs.GPBPUD.bit.GPIO39 = 1; // Enable pullup on GPIO39
GpioDataRegs.GPBSET.bit.GPIO39 = 1;// Load output latch to high
GpioCtrlRegs.GPBMUX1.bit.GPIO39 = 0; // GPIO39 = I/O
GpioCtrlRegs.GPBDIR.bit.GPIO39 = 1; // GPIO39 = output
GpioCtrlRegs.GPBPUD.bit.GPIO40 = 0; // Enable pullup on GPIO40
GpioDataRegs.GPBSET.bit.GPIO40 = 1;// Load output latch to high
GpioCtrlRegs.GPBMUX1.bit.GPIO40 = 0; // GPIO40 = I/O
GpioCtrlRegs.GPBDIR.bit.GPIO40 = 0; // GPIO40 = input
GpioCtrlRegs.GPBPUD.bit.GPIO58 = 1; // Enable pullup on GPIO58
GpioDataRegs.GPBSET.bit.GPIO58 = 1; // Load output latch to high
GpioCtrlRegs.GPBMUX2.bit.GPIO58 = 0; // GPIO58 = I/O
GpioCtrlRegs.GPBDIR.bit.GPIO58 = 1; // GPIO58 = output
GpioCtrlRegs.GPBPUD.bit.GPIO59 = 1; // Disable pullup on GPIO59
GpioDataRegs.GPBCLEAR.bit.GPIO59 = 1; // Load output latch to low
GpioCtrlRegs.GPBMUX2.bit.GPIO59 = 0; // GPIO59 = I/O
GpioCtrlRegs.GPBDIR.bit.GPIO59 = 1; // GPIO59 = output
EDIS;
}
void InitEPWM(void)
{
EALLOW;
CpuSysRegs.PCLKCR0.bit.TBCLKSYNC = 0; // Stop all the TB clocks
EDIS;
//ePWM1 INVPWM_NU&INVPWM_ND-----------------> PFC ISR
EALLOW;
EPwm1Regs.TZCTL.bit.TZA = 2; //force low
EPwm1Regs.TZCTL.bit.TZB = 2; //force low
EDIS;
EPwm1Regs.TBPRD = 2600; // Period = 5200 TBCLK counts 52us(19.2KHz)
EPwm1Regs.TBPHS.bit.TBPHS = 0; // Set Phase register to zero
EPwm1Regs.TBCTR = 0x0000; // Clear counter
EPwm1Regs.TBCTL.bit.CLKDIV = 0; // TBCLK = SYSCLKOUT / (HSPCLKDIV*CLKDIV)
EPwm1Regs.TBCTL.bit.HSPCLKDIV = 0;//=100M/(1*1)
EPwm1Regs.TBCTL.bit.CTRMODE = 2; //0--Up mode;1--Down mode;2--up-down mode
EPwm1Regs.TBCTL.bit.PHSEN = 0; //Do not load the time-base counter (TBCTR) from the time-base phase register (TBPHS)
EPwm1Regs.TBCTL.bit.PRDLD = 0;
EPwm1Regs.TBCTL.bit.SYNCOSEL = 3; // Disable EPWMxSYNCO signal
EPwm1Regs.CMPCTL.bit.SHDWAMODE = 0; //load CMPA from shadow register
EPwm1Regs.CMPCTL.bit.SHDWBMODE = 0; //load CMPB from shadow register
EPwm1Regs.CMPCTL.bit.LOADAMODE = 0; //load CMPA on CTR=0
EPwm1Regs.CMPCTL.bit.LOADBMODE = 0; //load CMPB on CTR=0
EPwm1Regs.CMPA.bit.CMPA = 0xFFFF;
EPwm1Regs.CMPB.bit.CMPB = 0xFFFF;
EPwm1Regs.DBCTL.bit.IN_MODE = 0;
EPwm1Regs.DBCTL.bit.POLSEL = 2;
EPwm1Regs.DBCTL.bit.OUT_MODE = 3; // ENALBE Dead-band module
EPwm1Regs.DBFED.bit.DBFED = 300;//280;//160;//280;//160; //deadband time
EPwm1Regs.DBRED.bit.DBRED = 300;//280;//160;//280;//160; //deadband time
EPwm1Regs.ETPS.bit.INTCNT = 0;
EPwm1Regs.ETPS.bit.INTPRD = 1;
EPwm1Regs.ETSEL.bit.INTEN = 1; //enable PWM int
EPwm1Regs.ETSEL.bit.INTSEL = 1;//Enable event time-base counter equal to zero.
EPwm1Regs.ETCLR.bit.INT = 1; //Clears the ETFLG[INT] flag bit
EPwm1Regs.AQCTLA.bit.CAU = 1;///1;
EPwm1Regs.AQCTLA.bit.CAD = 2;///2;
EPwm1Regs.AQCTLB.bit.CAU = 1;///1;
EPwm1Regs.AQCTLB.bit.CAD = 2;///2;
EPwm1Regs.AQCTLA.bit.ZRO = 0;
EPwm1Regs.AQCTLA.bit.PRD = 0;
EPwm1Regs.AQCTLB.bit.ZRO = 0;
EPwm1Regs.AQCTLB.bit.PRD = 0;
EPwm1Regs.AQCSFRC.bit.CSFA=1;
EPwm1Regs.AQSFRC.all=0x00c5;
EALLOW;
EPwm1Regs.TZFRC.bit.OST=1;
EDIS;
//ePWM2 INVPWM_LU&INVPWM_LD----------------> INV ISR
EALLOW;
EPwm2Regs.TZCTL.bit.TZA = 2; //force low
EPwm2Regs.TZCTL.bit.TZB = 2; //force low
EDIS;
EPwm2Regs.TBPRD = 2600; // Period = 5200 TBCLK counts 52us(19.2KHz)
EPwm2Regs.TBPHS.bit.TBPHS = 0; // Set Phase register to zero
EPwm2Regs.TBCTR = 0x0000; // Clear counter
EPwm2Regs.TBCTL.bit.CLKDIV = 0; // TBCLK = SYSCLKOUT / (HSPCLKDIV*CLKDIV)
EPwm2Regs.TBCTL.bit.HSPCLKDIV = 0;//=100M/(1*1)
EPwm2Regs.TBCTL.bit.CTRMODE = 2; //0--Up mode;1--Down mode;2--up-down mode
EPwm2Regs.TBCTL.bit.PHSEN = 0; //Do not load the time-base counter (TBCTR) from the time-base phase register (TBPHS)
EPwm2Regs.TBCTL.bit.PRDLD = 0;
EPwm2Regs.TBCTL.bit.SYNCOSEL = 3; // Disable EPWMxSYNCO signal
EPwm2Regs.CMPCTL.bit.SHDWAMODE = 0; //load CMPA from shadow register
EPwm2Regs.CMPCTL.bit.SHDWBMODE = 0; //load CMPB from shadow register
EPwm2Regs.CMPCTL.bit.LOADAMODE = 0; //load CMPA on CTR=0
EPwm2Regs.CMPCTL.bit.LOADBMODE = 0; //load CMPB on CTR=0
EPwm2Regs.CMPA.bit.CMPA = 0xFFFF;
EPwm2Regs.CMPB.bit.CMPB = 0xFFFF;
EPwm2Regs.DBCTL.bit.IN_MODE = 0;
EPwm2Regs.DBCTL.bit.POLSEL = 2;
EPwm2Regs.DBCTL.bit.OUT_MODE = 3; // ENALBE Dead-band module
EPwm2Regs.DBFED.bit.DBFED = 300;//280;//160;//280;//160; //deadband time
EPwm2Regs.DBRED.bit.DBRED = 300;//280;//160;//280;//160; //deadband time
// //Adc trigger
// EPwm2Regs.ETSEL.bit.SOCAEN = 1; // Enable SOC on A group
// EPwm2Regs.ETSEL.bit.SOCASEL = 2; // TBPRD
// EPwm2Regs.ETPS.bit.SOCAPRD = 1;
EPwm2Regs.ETPS.bit.INTCNT = 0;
EPwm2Regs.ETPS.bit.INTPRD = 1;
EPwm2Regs.ETSEL.bit.INTEN = 1; //enable PWM int
EPwm2Regs.ETSEL.bit.INTSEL = 2; ///2; //Enable event time-base counter equal to period.
EPwm2Regs.ETCLR.bit.INT = 1; //Clears the ETFLG[INT] flag bit
EPwm2Regs.AQCTLA.bit.CAU = 1;
EPwm2Regs.AQCTLA.bit.CAD = 2;
EPwm2Regs.AQCTLB.bit.CAU = 1;
EPwm2Regs.AQCTLB.bit.CAD = 2;
EPwm2Regs.AQCTLA.bit.ZRO = 0;
EPwm2Regs.AQCTLA.bit.PRD = 0;
EPwm2Regs.AQCTLB.bit.ZRO = 0;
EPwm2Regs.AQCTLB.bit.PRD = 0;
EALLOW;
EPwm2Regs.TZFRC.bit.OST=1;
EDIS;
EPwm2Regs.AQCSFRC.bit.CSFA=1;
EPwm2Regs.AQSFRC.all=0x00c5;
//ePWM3 DISCHG_1U&DISCHG_1D
EALLOW;
EPwm3Regs.TZCTL.bit.TZA = 2; //force low
EPwm3Regs.TZCTL.bit.TZB = 2; //force low
EDIS;
EPwm3Regs.TBPRD = 833; // Period = 1666 TBCLK counts 16.6us(60KHz)
EPwm3Regs.TBPHS.bit.TBPHS = 0; // Set Phase register to zero
EPwm3Regs.TBCTR = 0x0000; // Clear counter
EPwm3Regs.TBCTL.bit.CLKDIV = 0; // TBCLK = SYSCLKOUT / (HSPCLKDIV*CLKDIV)
EPwm3Regs.TBCTL.bit.HSPCLKDIV = 0;//=100M/(1*1)
EPwm3Regs.TBCTL.bit.CTRMODE = 2; //0--Up mode;1--Down mode;2--up-down mode
EPwm3Regs.TBCTL.bit.PHSEN = 0; //Do not load the time-base counter (TBCTR) from the time-base phase register (TBPHS)
EPwm3Regs.TBCTL.bit.PRDLD = 0;
EPwm3Regs.TBCTL.bit.SYNCOSEL = 3; // Disable EPWMxSYNCO signal
EPwm3Regs.CMPCTL.bit.SHDWAMODE = 0; //load CMPA from shadow register
EPwm3Regs.CMPCTL.bit.SHDWBMODE = 0; //load CMPB from shadow register
EPwm3Regs.CMPCTL.bit.LOADAMODE = 0; //load CMPA on CTR=0
EPwm3Regs.CMPCTL.bit.LOADBMODE = 0; //load CMPB on CTR=0
EPwm3Regs.CMPA.bit.CMPA = 0xFFFF;
EPwm3Regs.CMPB.bit.CMPB = 0xFFFF;
EPwm3Regs.DBCTL.bit.IN_MODE = 0;
EPwm3Regs.DBCTL.bit.POLSEL = 2;
EPwm3Regs.DBCTL.bit.OUT_MODE = 3; // ENALBE Dead-band module
EPwm3Regs.DBFED.bit.DBFED = 100;//1us //deadband time
EPwm3Regs.DBRED.bit.DBRED = 100;//1us //deadband time
EPwm3Regs.AQCTLA.bit.CAU = 1;
EPwm3Regs.AQCTLA.bit.CAD = 2;
EPwm3Regs.AQCTLB.bit.CAU = 1;
EPwm3Regs.AQCTLB.bit.CAD = 2;
EPwm3Regs.AQCTLA.bit.ZRO = 0;
EPwm3Regs.AQCTLA.bit.PRD = 0;
EPwm3Regs.AQCTLB.bit.ZRO = 0;
EPwm3Regs.AQCTLB.bit.PRD = 0;
EALLOW;
EPwm3Regs.TZFRC.bit.OST=1;
EDIS;
EPwm3Regs.AQCSFRC.bit.CSFA=1;
EPwm3Regs.AQSFRC.all=0x00c5;
//ePWM4 DISCHG_2U&DISCHG_2D
EALLOW;
EPwm4Regs.TZCTL.bit.TZA = 2; //force low
EPwm4Regs.TZCTL.bit.TZB = 2; //force low
EDIS;
EPwm4Regs.TBPRD = 833; // Period = 1666 TBCLK counts 16.6us(60KHz)
EPwm4Regs.TBPHS.bit.TBPHS = 0; // Set Phase register to zero
EPwm4Regs.TBCTR = 0x0000; // Clear counter
EPwm4Regs.TBCTL.bit.CLKDIV = 0; // TBCLK = SYSCLKOUT / (HSPCLKDIV*CLKDIV)
EPwm4Regs.TBCTL.bit.HSPCLKDIV = 0;//=100M/(1*1)
EPwm4Regs.TBCTL.bit.CTRMODE = 2; //0--Up mode;1--Down mode;2--up-down mode
EPwm4Regs.TBCTL.bit.PHSEN = 0; //Do not load the time-base counter (TBCTR) from the time-base phase register (TBPHS)
EPwm4Regs.TBCTL.bit.PRDLD = 0;
EPwm4Regs.TBCTL.bit.SYNCOSEL = 3; // Disable EPWMxSYNCO signal
EPwm4Regs.CMPCTL.bit.SHDWAMODE = 0; //load CMPA from shadow register
EPwm4Regs.CMPCTL.bit.SHDWBMODE = 0; //load CMPB from shadow register
EPwm4Regs.CMPCTL.bit.LOADAMODE = 0; //load CMPA on CTR=0
EPwm4Regs.CMPCTL.bit.LOADBMODE = 0; //load CMPB on CTR=0
EPwm4Regs.CMPA.bit.CMPA = 0xFFFF;
EPwm4Regs.CMPB.bit.CMPB = 0xFFFF;
EPwm4Regs.DBCTL.bit.IN_MODE = 0;
EPwm4Regs.DBCTL.bit.POLSEL = 2;
EPwm4Regs.DBCTL.bit.OUT_MODE = 3; // ENALBE Dead-band module
EPwm4Regs.DBFED.bit.DBFED = 100;//1us //deadband time
EPwm4Regs.DBRED.bit.DBRED = 100;//1us //deadband time
EPwm4Regs.AQCTLA.bit.CAU = 2;
EPwm4Regs.AQCTLA.bit.CAD = 1;
EPwm4Regs.AQCTLB.bit.CAU = 2;
EPwm4Regs.AQCTLB.bit.CAD = 1;
EPwm4Regs.AQCTLA.bit.ZRO = 0;
EPwm4Regs.AQCTLA.bit.PRD = 0;
EPwm4Regs.AQCTLB.bit.ZRO = 0;
EPwm4Regs.AQCTLB.bit.PRD = 0;
EALLOW;
EPwm4Regs.TZFRC.bit.OST=1;
EDIS;
EPwm4Regs.AQCSFRC.bit.CSFA=1;
EPwm4Regs.AQSFRC.all=0x00c5;
//ePWM5 CHG_PWM_U&CHG_PWM_D
EALLOW;
EPwm5Regs.TZCTL.bit.TZA = 2; //force low
EPwm5Regs.TZCTL.bit.TZB = 2; //force low
EDIS;
EPwm5Regs.TBPRD = 833; // Period = 1666 TBCLK counts 16.6us(60KHz)
EPwm5Regs.TBPHS.bit.TBPHS = 0; // Set Phase register to zero
EPwm5Regs.TBCTR = 0x0000; // Clear counter
EPwm5Regs.TBCTL.bit.CLKDIV = 0; // TBCLK = SYSCLKOUT / (HSPCLKDIV*CLKDIV)
EPwm5Regs.TBCTL.bit.HSPCLKDIV = 0;//=100M/(1*1)
EPwm5Regs.TBCTL.bit.CTRMODE = 2; //0--Up mode;1--Down mode;2--up-down mode
EPwm5Regs.TBCTL.bit.PHSEN = 0; //Do not load the time-base counter (TBCTR) from the time-base phase register (TBPHS)
EPwm5Regs.TBCTL.bit.PRDLD = 0;
EPwm5Regs.TBCTL.bit.SYNCOSEL = 3; // Disable EPWMxSYNCO signal
EPwm5Regs.CMPCTL.bit.SHDWAMODE = 0; //load CMPA from shadow register
EPwm5Regs.CMPCTL.bit.SHDWBMODE = 0; //load CMPB from shadow register
EPwm5Regs.CMPCTL.bit.LOADAMODE = 0; //load CMPA on CTR=0
EPwm5Regs.CMPCTL.bit.LOADBMODE = 0; //load CMPB on CTR=0
EPwm5Regs.CMPA.bit.CMPA = 0xFFFF;
EPwm5Regs.CMPB.bit.CMPB = 0xFFFF;
EPwm5Regs.DBCTL.bit.IN_MODE = 0;
EPwm5Regs.DBCTL.bit.POLSEL = 2;
EPwm5Regs.DBCTL.bit.OUT_MODE = 3; // ENALBE Dead-band module
EPwm5Regs.DBFED.bit.DBFED = 100; //1us //deadband time
EPwm5Regs.DBRED.bit.DBRED = 100; //1us//deadband time
EPwm5Regs.AQCTLA.bit.CAU = 1;
EPwm5Regs.AQCTLA.bit.CAD = 2;
EPwm5Regs.AQCTLB.bit.CAU = 1;
EPwm5Regs.AQCTLB.bit.CAD = 2;
EPwm5Regs.AQCTLA.bit.ZRO = 0;
EPwm5Regs.AQCTLA.bit.PRD = 0;
EPwm5Regs.AQCTLB.bit.ZRO = 0;
EPwm5Regs.AQCTLB.bit.PRD = 0;
EALLOW;
EPwm5Regs.TZFRC.bit.OST=1;
EDIS;
EPwm5Regs.AQCSFRC.bit.CSFA=1;
EPwm5Regs.AQSFRC.all=0x00c5;
//ePWM6 SftRly & FAN.SPEED
EPwm6Regs.TBPRD = 9999; //Period = (TBPRD+1)*0.01us = 100us (10KHz)
EPwm6Regs.TBPHS.bit.TBPHS = 0; // Set Phase register to zero
EPwm6Regs.TBCTR = 0x0000; // Clear counter
EPwm6Regs.TBCTL.bit.CLKDIV = 0; // TBCLK = SYSCLKOUT / (HSPCLKDIV*CLKDIV)
EPwm6Regs.TBCTL.bit.HSPCLKDIV = 0;//=100M/(1*1)
EPwm6Regs.TBCTL.bit.CTRMODE = 0; // up mode
EPwm6Regs.TBCTL.bit.PHSEN = 0; //Do not load the time-base counter (TBCTR) from the time-base phase register (TBPHS)
EPwm6Regs.TBCTL.bit.PRDLD = 0; //loaded from shadow register when TBCTR is equal to zero
EPwm6Regs.TBCTL.bit.SYNCOSEL = 3; // Disable EPWMxSYNCO signal
EPwm6Regs.CMPCTL.all = 0x0000; //CMPA&CMPB load from shadow register when CTR=0;
EPwm6Regs.AQCTLA.all=0x0012; //PWM6A(Sftrly):when = CMPA, force low,when=0, force high
EPwm6Regs.AQCTLB.all=0x0102;//PWM6B(FanSpeed):when = CMPB, force low,when=0, force high
EPwm6Regs.CMPA.bit.CMPA = 0x0000;//0x1D4C; //75%
EPwm6Regs.CMPB.bit.CMPB = 0x0ABD;
EPwm6Regs.DBCTL.bit.OUT_MODE = 0; // disable Dead-band module*/
//ePWM7 OpRly
EPwm7Regs.TBPRD = 9999; //Period = (TBPRD+1)*0.01us = 100us (10KHz)
EPwm7Regs.TBPHS.bit.TBPHS = 0; // Set Phase register to zero
EPwm7Regs.TBCTR = 0x0000; // Clear counter
EPwm7Regs.TBCTL.bit.CLKDIV = 0; // TBCLK = SYSCLKOUT / (HSPCLKDIV*CLKDIV)
EPwm7Regs.TBCTL.bit.HSPCLKDIV = 0;//=100M/(1*1)
EPwm7Regs.TBCTL.bit.CTRMODE = 0; // up mode
EPwm7Regs.TBCTL.bit.PHSEN = 0; //Do not load the time-base counter (TBCTR) from the time-base phase register (TBPHS)
EPwm7Regs.TBCTL.bit.PRDLD = 0; //loaded from shadow register when TBCTR is equal to zero
EPwm7Regs.TBCTL.bit.SYNCOSEL = 3; // Disable EPWMxSYNCO signal
EPwm7Regs.CMPCTL.all = 0x0000; //CMPA&CMPB load from shadow register when CTR=0;
EPwm7Regs.AQCTLA.all=0x0012; //PWM7A(Oprly):when = CMPA, force high,when=0, force low
EPwm7Regs.AQCTLB.all=0x0000;//PWM7B:LLCI.OCP
EPwm7Regs.CMPA.bit.CMPA = 0x0000;//0x1D4C; //75%
EPwm7Regs.CMPB.bit.CMPB = 0xffff;
EPwm7Regs.DBCTL.bit.OUT_MODE = 0; // disable Dead-band module*/
//ePWM8 PWM_BUCK
EPwm8Regs.TBPRD = 1300; //26us (38.4KHz)
EPwm8Regs.TBPHS.bit.TBPHS = 0; // Set Phase register to zero
EPwm8Regs.TBCTR = 0x0000; // Clear counter
EPwm8Regs.TBCTL.bit.CLKDIV = 0;//100M
EPwm8Regs.TBCTL.bit.HSPCLKDIV = 0;//100M
EPwm8Regs.TBCTL.bit.CTRMODE = 2; //0--Up mode;1--Down mode;2--up-down mode
EPwm8Regs.TBCTL.bit.PHSEN = 0; //Do not load the time-base counter (TBCTR) from the time-base phase register (TBPHS)
EPwm8Regs.TBCTL.bit.PRDLD = 0;
EPwm8Regs.TBCTL.bit.SYNCOSEL = 3; // Disable EPWMxSYNCO signal
EPwm8Regs.CMPCTL.bit.SHDWAMODE = 0; //load CMPA from shadow register
EPwm8Regs.CMPCTL.bit.SHDWBMODE = 0; //load CMPB from shadow register
EPwm8Regs.CMPCTL.bit.LOADAMODE = 0; //load CMPA on CTR=0
EPwm8Regs.CMPCTL.bit.LOADBMODE = 0; //load CMPB on CTR=0
EPwm8Regs.AQCTLA.all=0x0555;
EPwm8Regs.AQCTLB.all=0x0555;
EPwm8Regs.CMPA.bit.CMPA = 0xffff;
EPwm8Regs.CMPB.bit.CMPB = 0xffff;
EPwm8Regs.DBCTL.bit.OUT_MODE = 0; // disable Dead-band module
EALLOW;
CpuSysRegs.PCLKCR0.bit.TBCLKSYNC = 1; // Start all the timers synced
EDIS;
}
void InitECAP(void) //eCAP��SYSCLKΪʱ��
{
EALLOW;
InputXbarRegs.INPUT1SELECT = 25; //ʹ��INPUT1--GPIO25����
GpioCtrlRegs.GPADIR.bit.GPIO25 = 0; //��������
GpioCtrlRegs.GPAPUD.bit.GPIO25 = 0; //��������
GpioCtrlRegs.GPAQSEL2.bit.GPIO25 = 3; //GPIO����Ϊ��ͬ��ģʽ
InputXbarRegs.INPUT2SELECT = 26; //ʹ��INPUT2--GPIO26����
GpioCtrlRegs.GPADIR.bit.GPIO26 = 0; //��������
GpioCtrlRegs.GPAPUD.bit.GPIO26 = 0; //��������
GpioCtrlRegs.GPAQSEL2.bit.GPIO26 = 3; //GPIO����Ϊ��ͬ��ģʽ
InputXbarRegs.INPUT3SELECT = 27; //ʹ��INPUT3--GPIO27����
GpioCtrlRegs.GPADIR.bit.GPIO27 = 0; //��������
GpioCtrlRegs.GPAPUD.bit.GPIO27 = 0; //��������
GpioCtrlRegs.GPAQSEL2.bit.GPIO27 = 3; //GPIO����Ϊ��ͬ��ģʽ
EDIS;
EALLOW;
ECap1Regs.ECCTL0.bit.INPUTSEL = 0; //ECap1�������Ŷ�Ӧ��INTPUT1
ECap1Regs.ECEINT.all = 0x0000; // Disable all capture interrupts
ECap1Regs.ECCLR.all = 0xFFFF; // Clear all CAP interrupt flags
ECap1Regs.ECCTL1.bit.CAPLDEN = 1; //ʹ��װ��
ECap1Regs.ECCTL1.bit.CAP1POL = 1; // Falling edge
ECap1Regs.ECCTL1.bit.CTRRST1 = 0; // do not reset counter
ECap1Regs.ECCTL1.bit.PRESCALE = 0; // div= /1
ECap1Regs.ECCTL2.bit.TSCTRSTOP = 1; //ʱ�����������������
ECap1Regs.ECCTL2.bit.CAP_APWM = 0; // eCAP mode
ECap1Regs.ECCTL2.bit.CONT_ONESHT = 0; // one-shot mode
ECap1Regs.ECCTL2.bit.SYNCO_SEL = 3; // disable sync out signal
ECap1Regs.ECCTL2.bit.SYNCI_EN = 0; // disable synv in option
ECap1Regs.ECCTL2.bit.STOP_WRAP = 0; // Stop after Capture Event 1 in one-shot mode
ECap1Regs.ECCTL2.bit.REARM = 1; // arm one-shot
ECap1Regs.ECEINT.bit.CEVT1 = 1; // 1 events = interrupt
ECap2Regs.ECCTL0.bit.INPUTSEL = 1; //ECap2�������Ŷ�Ӧ��INTPUT2
ECap2Regs.ECEINT.all = 0x0000; // Disable all capture interrupts
ECap2Regs.ECCLR.all = 0xFFFF; // Clear all CAP interrupt flags
ECap2Regs.ECCTL1.bit.CAPLDEN = 1; //ʹ��װ��
ECap2Regs.ECCTL1.bit.CAP1POL = 1; // Falling edge
ECap2Regs.ECCTL1.bit.CTRRST1 = 0; // do not reset counter
ECap2Regs.ECCTL1.bit.PRESCALE = 0; // div= /1
ECap2Regs.ECCTL2.bit.TSCTRSTOP = 1; //ʱ�����������������
ECap2Regs.ECCTL2.bit.CAP_APWM = 0; // eCAP mode
ECap2Regs.ECCTL2.bit.CONT_ONESHT = 0; // one-shot mode
ECap2Regs.ECCTL2.bit.SYNCO_SEL = 3; // disable sync out signal
ECap2Regs.ECCTL2.bit.SYNCI_EN = 0; // disable synv in option
ECap2Regs.ECCTL2.bit.STOP_WRAP = 0; // Stop after Capture Event 1 in one-shot mode
ECap2Regs.ECCTL2.bit.REARM = 1; // arm one-shot
ECap2Regs.ECEINT.bit.CEVT1 = 1; // 1 events = interrupt
ECap3Regs.ECCTL0.bit.INPUTSEL = 2; //ECap2�������Ŷ�Ӧ��INTPUT2
ECap3Regs.ECEINT.all = 0x0000; // Disable all capture interrupts
ECap3Regs.ECCLR.all = 0xFFFF; // Clear all CAP interrupt flags
ECap3Regs.ECCTL1.bit.CAPLDEN = 1; //ʹ��װ��
ECap3Regs.ECCTL1.bit.CAP1POL = 1; // Falling edge
ECap3Regs.ECCTL1.bit.CTRRST1 = 0; // do not reset counter
ECap3Regs.ECCTL1.bit.PRESCALE = 0; // div= /1
ECap3Regs.ECCTL2.bit.TSCTRSTOP = 1; //ʱ�����������������
ECap3Regs.ECCTL2.bit.CAP_APWM = 0; // eCAP mode
ECap3Regs.ECCTL2.bit.CONT_ONESHT = 0; // one-shot mode
ECap3Regs.ECCTL2.bit.SYNCO_SEL = 3; // disable sync out signal
ECap3Regs.ECCTL2.bit.SYNCI_EN = 0; // disable synv in option
ECap3Regs.ECCTL2.bit.STOP_WRAP = 0; // Stop after Capture Event 1 in one-shot mode
ECap3Regs.ECCTL2.bit.REARM = 1; // arm one-shot
ECap3Regs.ECEINT.bit.CEVT1 = 1; // 1 events = interrupt
EDIS;
}
void InitADC(void)
{
// Setup VREF as internal
SetVREF(ADC_ADCA, ADC_INTERNAL, ADC_VREF3P3);
EALLOW;
// Set ADCCLK divider to /4
AdcaRegs.ADCCTL2.bit.PRESCALE = 6;
// Set pulse positions to late
AdcaRegs.ADCCTL1.bit.INTPULSEPOS = 1;
// Power up the ADC and then delay for 1 ms
AdcaRegs.ADCCTL1.bit.ADCPWDNZ = 1;
EDIS;
DELAY_US(1000);
EALLOW;
AdcaRegs.ADCCTL1.bit.INTPULSEPOS = 1; //ADCINT1 trips after AdcResults latch
AdcaRegs.ADCINTSEL1N2.bit.INT1E = 1; //Enabled ADCINT1
AdcaRegs.ADCINTSEL1N2.bit.INT1CONT = 0; //Disable ADCINT1 Continuous mode
AdcaRegs.ADCINTSEL1N2.bit.INT1SEL = 0xA; //setup EOC1 to trigger ADCINT1 to fire
AdcaRegs.ADCSOC0CTL.bit.CHSEL=0x0; //set SOC0 channel select to ADCINA0
AdcaRegs.ADCSOC1CTL.bit.CHSEL=0x1; //set SOC1channel select to ADCINA1
AdcaRegs.ADCSOC2CTL.bit.CHSEL=0x2; //set SOC2 channel select to ADCINA2
AdcaRegs.ADCSOC3CTL.bit.CHSEL=0x3; //set SOC3 channel select to ADCINA3
AdcaRegs.ADCSOC4CTL.bit.CHSEL=0x4; //set SOC4 channel select to ADCINA4
AdcaRegs.ADCSOC5CTL.bit.CHSEL=0x5; //set SOC5 channel select to ADCINA5
AdcaRegs.ADCSOC6CTL.bit.CHSEL=0x6; //set SOC6 channel select to ADCINA6
AdcaRegs.ADCSOC8CTL.bit.CHSEL=0x8; //set SOC8 channel select to ADCINA8
AdcaRegs.ADCSOC9CTL.bit.CHSEL=0x9; //set SOC9 channel select to ADCINA9
AdcaRegs.ADCSOC0CTL.bit.TRIGSEL=0x0;//set SOCXstart trigger on EPWM2A
AdcaRegs.ADCSOC1CTL.bit.TRIGSEL=0x0;
AdcaRegs.ADCSOC2CTL.bit.TRIGSEL=0x0;
AdcaRegs.ADCSOC3CTL.bit.TRIGSEL=0x0;
AdcaRegs.ADCSOC4CTL.bit.TRIGSEL=0x0;
AdcaRegs.ADCSOC5CTL.bit.TRIGSEL=0x0;
AdcaRegs.ADCSOC6CTL.bit.TRIGSEL=0x0;
AdcaRegs.ADCSOC8CTL.bit.TRIGSEL=0x0;
AdcaRegs.ADCSOC9CTL.bit.TRIGSEL=0x0;
AdcaRegs.ADCSOC0CTL.bit.ACQPS = 9; //set SOCX S/H Window to 10 ADC Clock Cycles
AdcaRegs.ADCSOC1CTL.bit.ACQPS = 9;
AdcaRegs.ADCSOC2CTL.bit.ACQPS = 9;
AdcaRegs.ADCSOC3CTL.bit.ACQPS = 9;
AdcaRegs.ADCSOC4CTL.bit.ACQPS = 9;
AdcaRegs.ADCSOC5CTL.bit.ACQPS = 9;
AdcaRegs.ADCSOC6CTL.bit.ACQPS = 9;
AdcaRegs.ADCSOC8CTL.bit.ACQPS = 9;
AdcaRegs.ADCSOC9CTL.bit.ACQPS = 9;
AdcaRegs.ADCINTFLGCLR.bit.ADCINT1 = 1;
EDIS;
SetVREF(ADC_ADCB, ADC_INTERNAL, ADC_VREF3P3);
EALLOW;
AdcbRegs.ADCCTL2.bit.PRESCALE = 6;
AdcbRegs.ADCCTL1.bit.INTPULSEPOS = 1;
AdcbRegs.ADCCTL1.bit.ADCPWDNZ = 1;
EDIS;
DELAY_US(1000);
EALLOW;
AdcbRegs.ADCCTL1.bit.INTPULSEPOS = 1; //ADCINT1 trips after AdcResults latch
AdcbRegs.ADCINTSEL1N2.bit.INT1E = 1; //Enabled ADCINT1
AdcbRegs.ADCINTSEL1N2.bit.INT1CONT = 0; //Disable ADCINT1 Continuous mode
AdcbRegs.ADCINTSEL1N2.bit.INT1SEL = 0x4; //setup EOC1 to trigger ADCINT1 to fire
AdcbRegs.ADCSOC0CTL.bit.CHSEL=0x0; //set SOC0 channel select to ADCINB0
// AdcbRegs.ADCSOC1CTL.bit.CHSEL=0x1; //set SOC1channel select to ADCINB1
AdcbRegs.ADCSOC2CTL.bit.CHSEL=0x2; //set SOC2 channel select to ADCINB2
AdcbRegs.ADCSOC3CTL.bit.CHSEL=0x3; //set SOC3 channel select to ADCINB3
AdcbRegs.ADCSOC4CTL.bit.CHSEL=0x4; //set SOC4 channel select to ADCINB4
AdcbRegs.ADCSOC0CTL.bit.TRIGSEL=0x0; //set SOCXstart trigger on EPWM2A
// AdcbRegs.ADCSOC1CTL.bit.TRIGSEL=0x0;
AdcbRegs.ADCSOC2CTL.bit.TRIGSEL=0x0;
AdcbRegs.ADCSOC3CTL.bit.TRIGSEL=0x0;
AdcbRegs.ADCSOC4CTL.bit.TRIGSEL=0x0;
AdcbRegs.ADCSOC0CTL.bit.ACQPS = 9; //set SOCX S/H Window to 10 ADC Clock Cycles
// AdcbRegs.ADCSOC1CTL.bit.ACQPS = 9;
AdcbRegs.ADCSOC2CTL.bit.ACQPS = 9;
AdcbRegs.ADCSOC3CTL.bit.ACQPS = 9;
AdcbRegs.ADCSOC4CTL.bit.ACQPS = 9;
AdcbRegs.ADCINTFLGCLR.bit.ADCINT1 = 1;
EDIS;
// Setup VREF as internal
SetVREF(ADC_ADCC, ADC_INTERNAL, ADC_VREF3P3);
EALLOW;
// Set ADCCLK divider to /4
AdccRegs.ADCCTL2.bit.PRESCALE = 6;
// Set pulse positions to late
AdccRegs.ADCCTL1.bit.INTPULSEPOS = 1;
// Power up the ADC and then delay for 1 ms
AdccRegs.ADCCTL1.bit.ADCPWDNZ = 1;
EDIS;
DELAY_US(1000);
EALLOW;
AdccRegs.ADCCTL1.bit.INTPULSEPOS = 1; //ADCINT1 trips after AdcResults latch
AdccRegs.ADCINTSEL1N2.bit.INT1E = 1; //Enabled ADCINT1
AdccRegs.ADCINTSEL1N2.bit.INT1CONT = 0; //Disable ADCINT1 Continuous mode
AdccRegs.ADCINTSEL1N2.bit.INT1SEL = 0xA; //setup EOC1 to trigger ADCINT1 to fire
// AdccRegs.ADCSOC0CTL.bit.CHSEL=0x0; //set SOC0 channel select to ADCINA0
// AdccRegs.ADCSOC1CTL.bit.CHSEL=0x1; //set SOC1channel select to ADCINA1
// AdccRegs.ADCSOC2CTL.bit.CHSEL=0x2; //set SOC2 channel select to ADCINA2
// AdccRegs.ADCSOC3CTL.bit.CHSEL=0x3; //set SOC3 channel select to ADCINA3
// AdccRegs.ADCSOC4CTL.bit.CHSEL=0x4; //set SOC4 channel select to ADCINA4
// AdccRegs.ADCSOC5CTL.bit.CHSEL=0x5; //set SOC5 channel select to ADCINA5
AdccRegs.ADCSOC10CTL.bit.CHSEL=0xA; //set SOC6 channel select to ADCINA6
// AdccRegs.ADCSOC15CTL.bit.CHSEL=0xF; //set SOC8 channel select to ADCINA8
// AdccRegs.ADCSOC0CTL.bit.TRIGSEL=0x0;//set SOCXstart trigger on EPWM2A
// AdccRegs.ADCSOC1CTL.bit.TRIGSEL=0x0;
// AdccRegs.ADCSOC2CTL.bit.TRIGSEL=0x0;
// AdccRegs.ADCSOC3CTL.bit.TRIGSEL=0x0;
// AdccRegs.ADCSOC4CTL.bit.TRIGSEL=0x0;
// AdccRegs.ADCSOC5CTL.bit.TRIGSEL=0x0;
AdccRegs.ADCSOC10CTL.bit.TRIGSEL=0x0;
// AdccRegs.ADCSOC15CTL.bit.TRIGSEL=0x0;
// AdccRegs.ADCSOC0CTL.bit.ACQPS = 9; //set SOCX S/H Window to 10 ADC Clock Cycles
// AdccRegs.ADCSOC1CTL.bit.ACQPS = 9;
// AdccRegs.ADCSOC2CTL.bit.ACQPS = 9;
// AdccRegs.ADCSOC3CTL.bit.ACQPS = 9;
// AdccRegs.ADCSOC4CTL.bit.ACQPS = 9;
// AdccRegs.ADCSOC5CTL.bit.ACQPS = 9;
AdccRegs.ADCSOC10CTL.bit.ACQPS = 9;
// AdccRegs.ADCSOC15CTL.bit.ACQPS = 9;
AdccRegs.ADCINTFLGCLR.bit.ADCINT1 = 1;
EDIS;
}
void InitSCI(void)
{
// One stop bit, no parity, 8-bit character length
SciaRegs.SCICCR.all = 0x07;
// Enable transmit and receive
SciaRegs.SCICTL1.all = 0x03;
// //19200
// //SciaRegs.SCIHBAUD.bit.BAUD = 0x02;
// //SciaRegs.SCILBAUD.bit.BAUD = 0x8A;
// //9600
// SciaRegs.SCIHBAUD.bit.BAUD = 0x05;
// SciaRegs.SCILBAUD.bit.BAUD = 0x15;
//
// SCIA at 9600 baud
// @LSPCLK = 25 MHz (100 MHz SYSCLK) HBAUD = 0x01 and LBAUD = 0x44.
//
SciaRegs.SCIHBAUD.all = 0x0001;
SciaRegs.SCILBAUD.all = 0x0044;
// Enable Receive interrupt and transmit interrupt
SciaRegs.SCICTL2.all = 0x03;
SciaRegs.SCICTL1.all = 0x0023; // Relinquish SCI from Reset
// One stop bit, no parity, 8-bit character length
ScibRegs.SCICCR.all = 0x07;
// Enable transmit and receive
ScibRegs.SCICTL1.all = 0x03;
//19200
ScibRegs.SCIHBAUD.bit.BAUD = 0x02;
ScibRegs.SCILBAUD.bit.BAUD = 0x8A;
// //9600 baud rate
// ScibRegs.SCIHBAUD.bit.BAUD = 0x05;
// ScibRegs.SCILBAUD.bit.BAUD = 0x15;
// Enable Receive interrupt and transmit interrupt
ScibRegs.SCICTL2.all = 0x03;
ScibRegs.SCICTL1.all = 0x0023; // Relinquish SCI from Reset
}
void InitCAN(void)
{
// // ��ʼ��CAN������
// CAN_initModule(CANA_BASE);
CanaRegs.CAN_CTL.bit.Init = 1;
CanaRegs.CAN_CTL.bit.PMD = 5;
CanaRegs.CAN_RAM_INIT.bit.CAN_RAM_INIT = 1;
CanaRegs.CAN_RAM_INIT.bit.KEY3 = 1;
CanaRegs.CAN_RAM_INIT.bit.KEY2 = 0;
CanaRegs.CAN_RAM_INIT.bit.KEY1 = 1;
CanaRegs.CAN_RAM_INIT.bit.KEY0 = 0;
while(CanaRegs.CAN_RAM_INIT.bit.RAM_INIT_DONE == 0)
{
}
EALLOW;
CanaRegs.CAN_CTL.bit.SWR = 1;
EDIS;
asm(" RPT #100 || NOP"); //delay 1us
CanaRegs.CAN_CTL.bit.CCE = 1;
// // ����CAN������Ϊ1MHz
// CAN_setBitRate(CANA_BASE, DEVICE_SYSCLK_FREQ, 1000000, 20);
CanaRegs.CAN_BTR.bit.BRP = 4;
CanaRegs.CAN_BTR.bit.SJW = 3;
CanaRegs.CAN_BTR.bit.TSEG1 = 10;
CanaRegs.CAN_BTR.bit.TSEG2 = 7;
CanaRegs.CAN_BTR.bit.BRPE = 0;
CanaRegs.CAN_CTL.bit.CCE = 0;
CanaRegs.CAN_CTL.bit.Init = 0;
// // ʹ��CAN�ж�
// CAN_enableInterrupt(CANA_BASE, CAN_INT_IE0 | CAN_INT_ERROR |CAN_INT_STATUS);
CanaRegs.CAN_CTL.bit.IE0 = 1;
CanaRegs.CAN_CTL.bit.EIE = 1;
CanaRegs.CAN_CTL.bit.SIE = 1;
// // ����CANA0�ж�
// Interrupt_register(INT_CANA0, &canISR);
// // ʹ��CANA0�ж�
// Interrupt_enable(INT_CANA0);
// CAN_enableGlobalInterrupt(CANA_BASE, CAN_GLOBAL_INT_CANINT0);
// // Initialize the transmit message object used for sending CAN messages.
// // Message Object Parameters:
// // Message Object ID Number: 1
// // Message Identifier: 0x1
// // Message Frame: Standard
// // Message Type: Transmit
// // Message ID Mask: 0x0
// // Message Object Flags: Transmit Interrupt
// // Message Data Length: 8 Bytes
// CAN_setupMessageObject(CANA_BASE, TX_MSG_OBJ_ID, CAN_ID, CAN_MSG_FRAME_STD,
// CAN_MSG_OBJ_TYPE_TX, 0, CAN_MSG_OBJ_TX_INT_ENABLE,
// MSG_DATA_LENGTH);
while(CanaRegs.CAN_IF1CMD.bit.Busy == 1)
{
}
CanaRegs.CAN_IF1ARB.bit.Dir = 1;
CanaRegs.CAN_IF1MSK.bit.Msk = 1;
CanaRegs.CAN_IF1MSK.bit.MDir = 1;
CanaRegs.CAN_IF1MCTL.bit.DLC = 8;
CanaRegs.CAN_IF1MCTL.bit.TxIE = 1;
CanaRegs.CAN_IF1MCTL.bit.RxIE = 1;
CanaRegs.CAN_IF1CMD.bit.Mask = 1;
CanaRegs.CAN_IF1CMD.bit.Arb = 1;
CanaRegs.CAN_IF1CMD.bit.Control = 1;
CanaRegs.CAN_IF1CMD.bit.DIR = 1;//0:read;1:write
// // Initialize the receive message object used for receiving CAN messages.
// // Message Object Parameters:
// // Message Object ID Number: 2
// // Message Identifier: 0x1
// // Message Frame: Standard
// // Message Type: Receive
// // Message ID Mask: 0x0
// // Message Object Flags: Receive Interrupt
// // Message Data Length: 8 Bytes
// CAN_setupMessageObject(CANA_BASE, RX_MSG_OBJ_ID, CAN_ID, CAN_MSG_FRAME_STD,
// CAN_MSG_OBJ_TYPE_RX, 0, CAN_MSG_OBJ_RX_INT_ENABLE,
// MSG_DATA_LENGTH);
while(CanaRegs.CAN_IF1CMD.bit.Busy == 1)
{
}
CanaRegs.CAN_IF1ARB.bit.Dir = 1;
CanaRegs.CAN_IF1MSK.bit.Msk = 1;
CanaRegs.CAN_IF1MSK.bit.MDir = 1;
CanaRegs.CAN_IF1MCTL.bit.DLC = 8;
CanaRegs.CAN_IF1MCTL.bit.TxIE = 1;
CanaRegs.CAN_IF1MCTL.bit.RxIE = 1;
CanaRegs.CAN_IF1CMD.bit.Mask = 1;
CanaRegs.CAN_IF1CMD.bit.Arb = 1;
CanaRegs.CAN_IF1CMD.bit.Control = 1;
CanaRegs.CAN_IF1CMD.bit.DIR = 0;//0:read;1:write
// // ���CANģ��
// CAN_startModule(CANA_BASE);
CanaRegs.CAN_CTL.bit.CCE = 0;
CanaRegs.CAN_CTL.bit.Init = 0;
// // ��ʼ��CAN������
// CAN_initModule(CANA_BASE);
//
// // ����CAN������Ϊ1MHz
// CAN_setBitRate(CANA_BASE, DEVICE_SYSCLK_FREQ, 1000000, 20);
//
// // ʹ��CAN�ж�
// CAN_enableInterrupt(CANA_BASE, CAN_INT_IE0 | CAN_INT_ERROR |
// CAN_INT_STATUS);
// // ����CANA0�ж�
// Interrupt_register(INT_CANA0, &canISR);
//
// // ʹ��CANA0�ж�
// Interrupt_enable(INT_CANA0);
// CAN_enableGlobalInterrupt(CANA_BASE, CAN_GLOBAL_INT_CANINT0);
//
// // Enable CAN test mode with external loopback
// // CAN_enableTestMode(CANA_BASE, CAN_TEST_EXL);
//
// //
// // Initialize the transmit message object used for sending CAN messages.
// // Message Object Parameters:
// // Message Object ID Number: 1
// // Message Identifier: 0x1
// // Message Frame: Standard
// // Message Type: Transmit
// // Message ID Mask: 0x0
// // Message Object Flags: Transmit Interrupt
// // Message Data Length: 8 Bytes
// //
// CAN_setupMessageObject(CANA_BASE, TX_MSG_OBJ_ID, CAN_ID, CAN_MSG_FRAME_STD,
// CAN_MSG_OBJ_TYPE_TX, 0, CAN_MSG_OBJ_TX_INT_ENABLE,
// MSG_DATA_LENGTH);
//
// //
// // Initialize the receive message object used for receiving CAN messages.
// // Message Object Parameters:
// // Message Object ID Number: 2
// // Message Identifier: 0x1
// // Message Frame: Standard
// // Message Type: Receive
// // Message ID Mask: 0x0
// // Message Object Flags: Receive Interrupt
// // Message Data Length: 8 Bytes
// //
// CAN_setupMessageObject(CANA_BASE, RX_MSG_OBJ_ID, CAN_ID, CAN_MSG_FRAME_STD,
// CAN_MSG_OBJ_TYPE_RX, 0, CAN_MSG_OBJ_RX_INT_ENABLE,
// MSG_DATA_LENGTH);
//
// // ���CANģ��
// CAN_startModule(CANA_BASE);
}
void InitPieINT(void)
{
//Enable PIE group 3 interrupt 1,2 for ePWM1,2,3
PieCtrlRegs.PIEIER3.bit.INTx1 = 1; //PFC
PieCtrlRegs.PIEIER3.bit.INTx2 = 1; //INV
//Enable PIE group 4 interrupt 1,2,3,4 for eCAP1,2,3,4
PieCtrlRegs.PIEIER4.bit.INTx1 = 1; //GridZero
PieCtrlRegs.PIEIER4.bit.INTx2 = 1; //INVZero
PieCtrlRegs.PIEIER4.bit.INTx3 = 1; //SYNRXD
//Enable PIE group 9
//interrupt 1,2 for SCIA
PieCtrlRegs.PIEIER9.bit.INTx1 = 1;
PieCtrlRegs.PIEIER9.bit.INTx2 = 1;
//interrupt 3,4 for SCIB
PieCtrlRegs.PIEIER9.bit.INTx3 = 1;
PieCtrlRegs.PIEIER9.bit.INTx4 = 1;
// //interrupt 5,6 for CANA
// PieCtrlRegs.PIEIER9.bit.INTx5 = 1;
// PieCtrlRegs.PIEIER9.bit.INTx6 = 1;
// //interrupt 7,8 for CANB
// PieCtrlRegs.PIEIER9.bit.INTx7 = 1;
// PieCtrlRegs.PIEIER9.bit.INTx8 = 1;
}
void DelayUs(volatile unsigned int Usec)
{
while(Usec--) // 1us loop at 100MHz CPUCLK
{
asm(" RPT #100 || NOP");
}
}
void sADCali(void)
{
unsigned long wChanASum[9];
unsigned long wChanBSum[5];
unsigned long wChanCSum[7];
unsigned int wSampleCnt;
volatile unsigned int *wP1;
volatile unsigned int *wP2;
volatile unsigned int *wP3;
int k,i,j;
wP1=(volatile unsigned int *)0x0B00; //pointer to Result 0 mirror register
wP2=(volatile unsigned int *)0x0B20;
wP3=(volatile unsigned int *)0x0B40;
DelayUs(20000); //delay 20ms
DelayUs(20000);
DelayUs(20000);
DelayUs(20000);
for(k = 0;k < 9;k++)
{
wChanASum[k] = 0; //clear buffer
}
for(i = 0;i < 5;i++)
{
wChanBSum[i] = 0; //clear buffer
}
for(j = 0;j < 7;j++)
{
wChanCSum[j] = 0; //clear buffer
}
for(wSampleCnt = 0;wSampleCnt < 32;wSampleCnt++)
{
mStartADAConvert(); //Start AD convert
asm(" RPT #100 || NOP"); //delay 1us
for(k = 0;k < 9;k++)
{
wChanASum[k]+=*(wP1+k); //read & sum AD result
}
AdcaRegs.ADCINTFLGCLR.bit.ADCINT1 = 1;//���EOC1�ź�(ADCINT1)
if(1 == AdcaRegs.ADCINTOVF.bit.ADCINT1) //ADCINT overflow occurred
{
AdcaRegs.ADCINTOVFCLR.bit.ADCINT1 = 1; //Clear overflow flag
AdcaRegs.ADCINTFLGCLR.bit.ADCINT1 = 1; //Re-clear ADCINT flag
}
mStartADBConvert();
for(i = 0;i < 5;i++)
{
wChanBSum[i]+=*(wP2+i); //read & sum AD result
}
AdcbRegs.ADCINTFLGCLR.bit.ADCINT1 = 1;
if(1 == AdcbRegs.ADCINTOVF.bit.ADCINT1) //ADCINT overflow occurred
{
AdcbRegs.ADCINTOVFCLR.bit.ADCINT1 = 1; //Clear overflow flag
AdcbRegs.ADCINTFLGCLR.bit.ADCINT1 = 1; //Re-clear ADCINT flag
}
mStartADCConvert();
for(j = 0;j < 7;j++)
{
wChanCSum[j]+=*(wP3+j); //read & sum AD result
}
AdccRegs.ADCINTFLGCLR.bit.ADCINT1 = 1;
if(1 == AdccRegs.ADCINTOVF.bit.ADCINT1) //ADCINT overflow occurred
{
AdccRegs.ADCINTOVFCLR.bit.ADCINT1 = 1; //Clear overflow flag
AdccRegs.ADCINTFLGCLR.bit.ADCINT1 = 1; //Re-clear ADCINT flag
}
}
wGridVolt_Bias = (int)((long)wChanASum[0]>>5);
wOpCurr_Bias = (int)((long)wChanASum[1]>>5);
wInvVolt_Bias = (int)((long)wChanASum[3]>>5);
wInvCurr_Bias = (int)((long)wChanASum[4]>>5);
wBusVolt_Bias = (int)((long)wChanASum[6]>>5);
wLowLoadCurr_Bias = (int)((long)wChanASum[7]>>5);
wLlcI_Bias = (int)((long)wChanASum[8]>>5);
wBatVolt_Bias = (int)((long)wChanBSum[0]>>5);
wTxtTemp_Bias = (int)((long)wChanBSum[1]>>5);
wInvTemp_Bias = (int)((long)wChanBSum[2]>>5);
wBusCurr_Bias = (int)((long)wChanBSum[3]>>5);
wBatTemp_Bias = (int)((long)wChanBSum[4]>>5);
}
