TMS320F28379D: GPIO INPUT SPEED

TJ,

The GPIO INPUT TIMING is in the very next section 8.9.6.2:

With QUALPRD=0, the GPIO requires the input signal to be held for 2 x SYSCLK cycles.

-Tommy

Well....yes.  The time would be 2 x 1 / SYSCLK.

SYSCLK is determined through software configuration (and board design if using an external clock source):

-Tommy

TJ,

That would be covered by footnote (2) from the GPIO Input Timing Requirements:

(2) For tw(GPI), pulse width is measured from VIL to VIL for an active low signal and VIH to VIH for an active high signal.

Being an asynchronous digital input, the primary factor is the voltage level of the input signal.

-Tommy

It would probably be easier to absorb through text with visualizations rather than to have someone verbally describe: https://learn.sparkfun.com/tutorials/logic-levels/