Hello,
I have a particular use case where I want to be sure the FIFO is fully loaded before I start the exchange with the slave (CPU is MASTER).
The reason is, as the peripheral frame is shared with the DMA, I have to ensure the words are in the FIFO to be sure I respect the protocol awaited by that salve.
Is there a way to achieve that ?
I have the feeling, from the registers fields descriptions, that this is not something feasible.
Best regards,
Clément