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TMS320F28379D: Unrecognized token error or expected an expression.

Part Number: TMS320F28379D

I am trying to generate phase shifted epwm using '3 moving averaged adc signals'. EPWM1 - master module. EPWM2 phase shifted by D1 from EPWM1. EPWM4 and EPWM 5 are phase shifted by D from EPWM1 and EPWM6 is phase shifted by D2 from EPWM5. ADCB2 is used as interrupt. EOC3 with clear ADCINT2 flag. The EPWM modules and ADC was running fine with continuous update. But after modifying the code for moving averaged, it is showing error. I have presented total code, so that you can be able to see the errors while running the code. I assume I am missing something very simple but can't figure it out.

//###########################################################################
//
// FILE:    epwm_deadband_c28.c
//
// TITLE:   Check PWM Dead-Band
//
//! \addtogroup cpu01_example_list
//! <h1> EPWM dead band control (epwm_deadband)</h1>
//!
//! During the test, monitor ePWM1, ePWM2, and/or ePWM3 outputs
//! on a scope.
//!
//! - ePWM1A is on GPIO0
//! - ePWM1B is on GPIO1
//! - ePWM2A is on GPIO2
//! - ePWM2B is on GPIO3
//! - ePWM3A is on GPIO4
//! - ePWM3B is on GPIO5
//!
//! This example configures ePWM1, ePWM2 and ePWM3 for:
//! - Count up/down
//! - Deadband
//!
//! 3 Examples are included:
//! - ePWM1: Active low PWMs
//! - ePWM2: Active low complementary PWMs
//! - ePWM3: Active high complementary PWMs
//!
//! Each ePWM is configured to interrupt on the 3rd zero event.
//! When this happens the deadband is modified such that
//! 0 <= DB <= DB_MAX.  That is, the deadband will move up and
//! down between 0 and the maximum value.
//!
//! View the EPWM1A/B, EPWM2A/B and EPWM3A/B waveforms
//! via an oscilloscope
//
//
//###########################################################################
// $TI Release: F2837xD Support Library v3.12.00.00 $
// $Release Date: Fri Feb 12 19:03:23 IST 2021 $
// $Copyright:
// Copyright (C) 2013-2021 Texas Instruments Incorporated - http://www.ti.com/
//
// Redistribution and use in source and binary forms, with or without 
// modification, are permitted provided that the following conditions 
// are met:
// 
//   Redistributions of source code must retain the above copyright
//   notice, this list of conditions and the following disclaimer.
// 
//   Redistributions in binary form must reproduce the above copyright
//   notice, this list of conditions and the following disclaimer in the
//   documentation and/or other materials provided with the
//   distribution.
// 
//   Neither the name of Texas Instruments Incorporated nor the names of
//   its contributors may be used to endorse or promote products derived
//   from this software without specific prior written permission.
// 
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 
// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 
// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 
// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 
// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 
// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
// $
//###########################################################################

//
// Included Files
//
#include "F28x_Project.h"



//Defines
#define D12_BUFFER 20
#define D_BUFFER 5
//
//
//
// Globals
//
Uint16 Mode_current;
Uint16 D1;
Uint16 D2;
Uint16 D;
Uint16 D1_adcb1;
Uint16 D2_adcb2;
Uint16 D_adcb3;
Uint16 D1_adcbresult1[D12_BUFFER];
Uint16 D2_adcbresult2[D12_BUFFER];
Uint16 D_adcbresult3[D_BUFFER];
Uint16 indexD12;
Uint16 indexD;


//
// Function Prototypes
//Here for simple DAB we will use EPWM1, EPWM2, EPWM4, EPWM5, EPWM6

void InitEPwm1Example(void);
void InitEPwm2Example(void);
void InitEPwm3Example(void);
void InitEPwm4Example(void);
void InitEPwm5Example(void);
void InitEPwm6Example(void);
void InitEPwm7Example(void);

void ConfigureADC(void);
void SetupADCSoftware(void);

__interrupt void adcb2_isr(void);


//
// Main
//
void main(void)
{
//
// Step 1. Initialize System Control:
// PLL, WatchDog, enable Peripheral Clocks
// This example function is found in the F2837xD_SysCtrl.c file.
//
    InitSysCtrl();

//
// Step 2. Initialize GPIO:
// This example function is found in the F2837xD_Gpio.c file and
// illustrates how to set the GPIO to its default state.
//
    InitGpio();

//
// enable PWM1, PWM2 and PWM3
//
    CpuSysRegs.PCLKCR2.bit.EPWM1=1;
    CpuSysRegs.PCLKCR2.bit.EPWM2=1;
    CpuSysRegs.PCLKCR2.bit.EPWM3=1;
    CpuSysRegs.PCLKCR2.bit.EPWM4=1;
    CpuSysRegs.PCLKCR2.bit.EPWM5=1;
    CpuSysRegs.PCLKCR2.bit.EPWM6=1;
    CpuSysRegs.PCLKCR2.bit.EPWM7=1;

//
// For this case just init GPIO pins for ePWM1, ePWM2, ePWM3
// These functions are in the F2837xD_EPwm.c file
//
    InitEPwm1Gpio();
    InitEPwm2Gpio();
    InitEPwm3Gpio();
    InitEPwm4Gpio();
    InitEPwm5Gpio();
    InitEPwm6Gpio();
    InitEPwm7Gpio();

//
// Step 3. Clear all interrupts and initialize PIE vector table:
// Disable CPU interrupts
//
    DINT;

//
// Initialize the PIE control registers to their default state.
// The default state is all PIE interrupts disabled and flags
// are cleared.
// This function is found in the F2837xD_PieCtrl.c file.
//
    InitPieCtrl();

//
// Disable CPU interrupts and clear all CPU interrupt flags:
//
    IER = 0x0000;
    IFR = 0x0000;

//
// Initialize the PIE vector table with pointers to the shell Interrupt
// Service Routines (ISR).
// This will populate the entire table, even if the interrupt
// is not used in this example.  This is useful for debug purposes.
// The shell ISR routines are found in F2837xD_DefaultIsr.c.
// This function is found in F2837xD_PieVect.c.
//
    InitPieVectTable();

//
// Interrupts that are used in this example are re-mapped to
// ISR functions found within this file.
//
    EALLOW; // This is needed to write to EALLOW protected registers
    PieVectTable.ADCB2_INT = &adcb2_isr;
    EDIS;   // This is needed to disable write to EALLOW protected registers

//
// Step 4. Initialize the Device Peripherals:
//
    EALLOW;
    CpuSysRegs.PCLKCR0.bit.TBCLKSYNC =0;
    EDIS;

    InitEPwm1Example();
    InitEPwm2Example();
    InitEPwm3Example();
    InitEPwm4Example();
    InitEPwm5Example();
    InitEPwm6Example();
    InitEPwm7Example();



//
// Step 5. User specific code, enable interrupts:
// Initialize counters:
//

//
// Enable CPU INT10 which is connected to ADCB2 INT:
//

    IER |= M_INT10;

//
// Enable ADCB2 INTn in the PIE: Group 10 interrupt 6
//

    PieCtrlRegs.PIEIER10.bit.INTx6 = 1;

//
// Enable global Interrupts and higher priority real-time debug events:
//
    EINT;  // Enable Global interrupt INTM
    ERTM;  // Enable Global realtime interrupt DBGM


//
//
// Initialize results buffer
//
    for(indexD12 = 0; indexD12 < D12_BUFFER; indexD12++)
    {
        D1_adcbresult1[indexD12] = 0;
        D2_adcbresult2[indexD12] = 0;
    }
    for(indexD = 0; indexD < D_BUFFER; indexD++)
    {
        D_adcbresult3[indexD] = 0;
    }
     indexD12 = 0;
     indexD   = 0;
     D1_adcb1 = 2500;
     D2_adcb2 = 2500;
     D_adcb3 = 10;
     D1 = 2500;
     D2 = 2500;
     D = 10;

// Setup ADC

     ConfigureADC();
     SetupADCSoftware();

//
    //start ePWM
    //
    EPwm3Regs.ETSEL.bit.SOCAEN = 1;  //enable SOCA
    EPwm3Regs.TBCTL.bit.CTRMODE = TB_COUNT_DOWN; //unfreeze, and enter down count mode

    EALLOW;
    CpuSysRegs.PCLKCR0.bit.TBCLKSYNC =1;
    EDIS;
//
// Step 6. IDLE loop. Just sit and loop forever (optional):
//
    do
        {
            //
            // Wait while ePWM causes ADC conversions.
            // ADCA1 ISR processes each new set of conversions.
            //
        }
        while(1);
}


//
// adcb2_isr
//
__interrupt void adcb2_isr(void)
 {   Uint16 i;
     Mode_current          = AdcbResultRegs.ADCRESULT0;
     D1_adcbresult1[indexD12] = AdcbResultRegs.ADCRESULT1;
     D2_adcbresult2[indexD12++] = AdcbResultRegs.ADCRESULT2;
     D_adcbresult3[indexD++]  = AdcbResultRegs.ADCRESULT3;

     if (indexD12 >= D12_BUFFER)
     {   indexD12 = 0;
         D1_adcb1 = 0;
         D2_adcb2 = 0;
         for(i = 0; i < D12_BUFFER; i++)
         {D1_adcb1 = D1_adcb1 + D1_adcbresult1[i];
          D2_adcb2 = D2_adcb2 + D2_adcbresult2[i];
         }
         D1_adcb1 = D1_adcb1/D12_BUFFER;
         D2_adcb2 = D2_adcb2/D12_BUFFER;

         D1 = D1_adcb1 * 0.6297; // 0.6297 is the calculated factor required to match the adcin results and TBPHS register
         D2 = D2_adcb2 * 0.6297;
     }


       //Limiter for D1 and D2
         if (D1 < 750)
         {D1 = 750;
         }
         else if (D1 > 2500)
         {D1 = 2500;
         }

         if (D2 < 750)
         {D2 = 750;
         }
         else if (D2 > 2500)
         {D2 = 2500;
         }
 //
 //
     if (indexD >= D_BUFFER)
      {  indexD = 0;
         D_adcb3 = 0;
         for(i = 0; i < D_BUFFER; i++)
           {D_adcb3 = D_adcb3 + D_adcbresult3[i];
           }
           D_adcb3 = D_adcb3/D_BUFFER;

           D_adcb3  = D_adcb3 * 0.3148;
      }// 0.3148 is the calculated factor required to match the adcin results and TBPHS register
     if (Mode_current > 2024)
     { D = D_adcb3;
     if (D > 1125)
     {D =1125;
      }}
     else
    { D = 4999-D_adcb3;
     if (D < 4249)
     {D =4249;
    }}




    EPwm2Regs.TBPHS.bit.TBPHS = D1;
    EPwm4Regs.TBPHS.bit.TBPHS = D;
    EPwm5Regs.TBPHS.bit.TBPHS = D;
    EPwm6Regs.TBPHS.bit.TBPHS = D2;

     //
     // Clear INT flag for this timer
     //
         AdcbRegs.ADCINTFLGCLR.bit.ADCINT2 = 1; //clear INT2 flag
     //
     //


    //
    // Acknowledge this interrupt to receive more interrupts from group 3
    //
    PieCtrlRegs.PIEACK.all = PIEACK_GROUP10;
}

//
// InitEPwm1Example - Initialize EPWM1 configuration
//
void InitEPwm1Example()
{
    EPwm1Regs.TBPRD = 4999;                       // Set timer period
    EPwm1Regs.TBPHS.bit.TBPHS = 0x0000;           // Phase is 0
    EPwm1Regs.TBCTR = 0x0000;                     // Clear counter

    //
    // Setup TBCLK
    //
    EPwm1Regs.TBCTL.bit.CTRMODE = TB_COUNT_DOWN; // Count down
    EPwm1Regs.TBCTL.bit.PHSEN = TB_DISABLE;        // Disable phase loading
    EPwm1Regs.TBCTL.bit.HSPCLKDIV = TB_DIV2;       // Clock ratio to SYSCLKOUT
    EPwm1Regs.TBCTL.bit.CLKDIV = TB_DIV1;
    EPwm1Regs.TBCTL.bit.SYNCOSEL = TB_CTR_ZERO;

    EPwm1Regs.CMPCTL.bit.SHDWAMODE = CC_SHADOW;    // Load registers every ZERO
    EPwm1Regs.CMPCTL.bit.SHDWBMODE = CC_SHADOW;
    EPwm1Regs.CMPCTL.bit.LOADAMODE = CC_CTR_ZERO;
    EPwm1Regs.CMPCTL.bit.LOADBMODE = CC_CTR_ZERO;

    //
    // Setup compare
    //
    EPwm1Regs.CMPA.bit.CMPA = 2500;

    //
    // Set actions
    //
    EPwm1Regs.AQCTLA.bit.ZRO = AQ_CLEAR;            // Set PWM1A on CMPA and reset at ZRO
    EPwm1Regs.AQCTLA.bit.CAD = AQ_SET;

    //
    // Active High Complementary
    //
    EPwm1Regs.DBCTL.bit.OUT_MODE = DB_DISABLE;      // Disable deadband since gate driver have its own
    //EPwm1Regs.DBCTL.bit.POLSEL = DB_ACTV_HIC;
    //EPwm1Regs.DBCTL.bit.IN_MODE = DBA_ALL;
    //EPwm1Regs.DBRED.bit.DBRED = EPWM_DB;
    //EPwm1Regs.DBFED.bit.DBFED = EPWM_DB;


}

//
// InitEPwm2Example - Initialize EPWM2 configuration
//
void InitEPwm2Example()
{
    EPwm2Regs.TBPRD = 4999;                       // Set timer period
    EPwm2Regs.TBPHS.bit.TBPHS = 2500;               // Phase is 0
    EPwm2Regs.TBCTR = 0x0000;                     // Clear counter

    //
    // Setup TBCLK
    //
    EPwm2Regs.TBCTL.bit.CTRMODE = TB_COUNT_DOWN; // Count down
    EPwm2Regs.TBCTL.bit.PHSEN = TB_ENABLE;        // Disable phase loading
    EPwm2Regs.TBCTL.bit.HSPCLKDIV = TB_DIV2;       // Clock ratio to SYSCLKOUT
    EPwm2Regs.TBCTL.bit.CLKDIV = TB_DIV1;
    EPwm2Regs.TBCTL.bit.SYNCOSEL = TB_SYNC_IN;

    EPwm2Regs.CMPCTL.bit.SHDWAMODE = CC_SHADOW;    // Load registers every ZERO
    EPwm2Regs.CMPCTL.bit.SHDWBMODE = CC_SHADOW;
    EPwm2Regs.CMPCTL.bit.LOADAMODE = CC_CTR_ZERO;
    EPwm2Regs.CMPCTL.bit.LOADBMODE = CC_CTR_ZERO;

    //
    // Setup compare
    //
    EPwm2Regs.CMPA.bit.CMPA = 2500;

    //
    // Set actions
    //
    EPwm2Regs.AQCTLA.bit.ZRO = AQ_CLEAR;            // Set PWM2A on Zero
    EPwm2Regs.AQCTLA.bit.CAD = AQ_SET;

    //
    // Active High Complementary
    //
    EPwm2Regs.DBCTL.bit.OUT_MODE = DB_DISABLE;
    //EPwm2Regs.DBCTL.bit.POLSEL = DB_ACTV_HIC;
    //EPwm2Regs.DBCTL.bit.IN_MODE = DBA_ALL;
    //EPwm2Regs.DBRED.bit.DBRED = EPWM_DB;
    //EPwm2Regs.DBFED.bit.DBFED = EPWM_DB;
}

// EPWM3 will be unused.
// InitEPwm3Example - Initialize EPWM2 configuration
//
void InitEPwm3Example()
{
    EPwm3Regs.TBPRD = 4999;                       // Set timer period
    EPwm3Regs.TBPHS.bit.TBPHS = 0x0000;                // Phase is 0
    EPwm3Regs.TBCTR = 0x0000;                     // Clear counter

    //
    // Setup TBCLK
    //
    EPwm3Regs.TBCTL.bit.PHSEN = TB_ENABLE;        // Disable phase loading
    EPwm3Regs.TBCTL.bit.HSPCLKDIV = TB_DIV2;       // Clock ratio to SYSCLKOUT
    EPwm3Regs.TBCTL.bit.CLKDIV = TB_DIV1;
    EPwm3Regs.TBCTL.bit.SYNCOSEL = TB_SYNC_IN;

    EPwm3Regs.CMPCTL.bit.SHDWAMODE = CC_SHADOW;    // Load registers every ZERO
    EPwm3Regs.CMPCTL.bit.SHDWBMODE = CC_SHADOW;
    EPwm3Regs.CMPCTL.bit.LOADAMODE = CC_CTR_ZERO;
    EPwm3Regs.CMPCTL.bit.LOADBMODE = CC_CTR_ZERO;

    //
    // Setup compare
    //
    EPwm3Regs.CMPA.bit.CMPA = 2500;

    //
    // Set actions
    //
    EPwm3Regs.AQCTLA.bit.ZRO = AQ_CLEAR;            // Set PWM1A on Zero
    EPwm3Regs.AQCTLA.bit.CAD = AQ_SET;

    //
    // Active High Complementary
    //
    EPwm3Regs.DBCTL.bit.OUT_MODE = DB_DISABLE;
    //EPwm3Regs.DBCTL.bit.POLSEL = DB_ACTV_HIC;
    //EPwm3Regs.DBCTL.bit.IN_MODE = DBA_ALL;
    //EPwm3Regs.DBRED.bit.DBRED = EPWM_DB;
    //EPwm3Regs.DBFED.bit.DBFED = EPWM_DB;

    //
   // start SOC
   //
    EPwm3Regs.ETSEL.bit.SOCAEN    = 0;    // Disable SOC on A group
    EPwm3Regs.ETSEL.bit.SOCASEL    = 5;   // Select SOC on down-count
    EPwm3Regs.ETPS.bit.SOCAPRD = 1;       // Generate pulse on 1st event
    EPwm3Regs.TBCTL.bit.CTRMODE = TB_FREEZE; // FREEZE
}

//
// InitEPwm4Example - Initialize EPWM2 configuration
//
void InitEPwm4Example()
{
    SyncSocRegs.SYNCSELECT.bit.EPWM4SYNCIN = 0;   //EPWM1SYNCOUT
    EPwm4Regs.TBPRD = 4999;                       // Set timer period
    EPwm4Regs.TBPHS.bit.TBPHS = 0;           // Phase is D
    EPwm4Regs.TBCTR = 0x0000;                     // Clear counter

    //
    // Setup TBCLK
    //
    EPwm4Regs.TBCTL.bit.CTRMODE = TB_COUNT_DOWN; // Count down
    EPwm4Regs.TBCTL.bit.PHSEN = TB_ENABLE;        // Disable phase loading
    EPwm4Regs.TBCTL.bit.HSPCLKDIV = TB_DIV2;       // Clock ratio to SYSCLKOUT
    EPwm4Regs.TBCTL.bit.CLKDIV = TB_DIV1;
    EPwm4Regs.TBCTL.bit.SYNCOSEL = TB_SYNC_IN;   //It should be set to zero

    EPwm4Regs.CMPCTL.bit.SHDWAMODE = CC_SHADOW;    // Load registers every ZERO
    EPwm4Regs.CMPCTL.bit.SHDWBMODE = CC_SHADOW;
    EPwm4Regs.CMPCTL.bit.LOADAMODE = CC_CTR_ZERO;
    EPwm4Regs.CMPCTL.bit.LOADBMODE = CC_CTR_ZERO;

    //
    // Setup compare
    //
    EPwm4Regs.CMPA.bit.CMPA = 2500;

    //
    // Set actions
    //
    EPwm4Regs.AQCTLA.bit.ZRO = AQ_CLEAR;            // Set PWM4A on Zero
    EPwm4Regs.AQCTLA.bit.CAD = AQ_SET;


    //
    // Active High Complementary
    //
    EPwm4Regs.DBCTL.bit.OUT_MODE = DB_DISABLE;
    //EPwm4Regs.DBCTL.bit.POLSEL = DB_ACTV_HIC;
    //EPwm4Regs.DBCTL.bit.IN_MODE = DBA_ALL;
    //EPwm4Regs.DBRED.bit.DBRED = EPWM_DB;
    //EPwm4Regs.DBFED.bit.DBFED = EPWM_DB;
}

//
// InitEPwm5Example - Initialize EPWM2 configuration
//
void InitEPwm5Example()
{
    EPwm5Regs.TBPRD = 4999;                       // Set timer period
    EPwm5Regs.TBPHS.bit.TBPHS = 0;               // Phase is D
    EPwm5Regs.TBCTR = 0x0000;                     // Clear counter

    //
    // Setup TBCLK
    //
    EPwm5Regs.TBCTL.bit.CTRMODE = TB_COUNT_DOWN;  // Count down
    EPwm5Regs.TBCTL.bit.PHSEN = TB_ENABLE;        // Disable phase loading
    EPwm5Regs.TBCTL.bit.HSPCLKDIV = TB_DIV2;       // Clock ratio to SYSCLKOUT
    EPwm5Regs.TBCTL.bit.CLKDIV = TB_DIV1;
    EPwm5Regs.TBCTL.bit.SYNCOSEL = TB_CTR_ZERO;

    EPwm5Regs.CMPCTL.bit.SHDWAMODE = CC_SHADOW;    // Load registers every ZERO
    EPwm5Regs.CMPCTL.bit.SHDWBMODE = CC_SHADOW;
    EPwm5Regs.CMPCTL.bit.LOADAMODE = CC_CTR_ZERO;
    EPwm5Regs.CMPCTL.bit.LOADBMODE = CC_CTR_ZERO;

    //
    // Setup compare
    //
    EPwm5Regs.CMPA.bit.CMPA = 2500;

    //
    // Set actions
    //
    EPwm5Regs.AQCTLA.bit.ZRO = AQ_CLEAR;            // Set PWM1A on Zero
    EPwm5Regs.AQCTLA.bit.CAD = AQ_SET;

    //
    // Active High Complementary
    //
    EPwm5Regs.DBCTL.bit.OUT_MODE = DB_DISABLE;
    //EPwm5Regs.DBCTL.bit.POLSEL = DB_ACTV_HIC;
    //EPwm5Regs.DBCTL.bit.IN_MODE = DBA_ALL;
    //EPwm5Regs.DBRED.bit.DBRED = EPWM_DB;
    //EPwm5Regs.DBFED.bit.DBFED = EPWM_DB;
}

//
// InitEPwm6Example - Initialize EPWM2 configuration
//
void InitEPwm6Example()
{
    EPwm6Regs.TBPRD = 4999;                       // Set timer period
    EPwm6Regs.TBPHS.bit.TBPHS = 0;           // Phase is 0
    EPwm6Regs.TBCTR = 0x0000;                     // Clear counter

    //
    // Setup TBCLK
    //
    EPwm6Regs.TBCTL.bit.CTRMODE = TB_COUNT_DOWN; // Count down
    EPwm6Regs.TBCTL.bit.PHSEN = TB_ENABLE;        // Disable phase loading
    EPwm6Regs.TBCTL.bit.HSPCLKDIV = TB_DIV2;       // Clock ratio to SYSCLKOUT
    EPwm6Regs.TBCTL.bit.CLKDIV = TB_DIV1;
    EPwm6Regs.TBCTL.bit.SYNCOSEL = TB_SYNC_IN;

    EPwm6Regs.CMPCTL.bit.SHDWAMODE = CC_SHADOW;    // Load registers every ZERO
    EPwm6Regs.CMPCTL.bit.SHDWBMODE = CC_SHADOW;
    EPwm6Regs.CMPCTL.bit.LOADAMODE = CC_CTR_ZERO;
    EPwm6Regs.CMPCTL.bit.LOADBMODE = CC_CTR_ZERO;

    //
    // Setup compare
    //
    EPwm6Regs.CMPA.bit.CMPA = 2500;

    //
    // Set actions
    //
    EPwm6Regs.AQCTLA.bit.ZRO = AQ_CLEAR;            // Set PWM6A on Zero
    EPwm6Regs.AQCTLA.bit.CAD = AQ_SET;

    //
    // Active High Complementary
    //
    EPwm6Regs.DBCTL.bit.OUT_MODE = DB_FULL_ENABLE;
    //EPwm6Regs.DBCTL.bit.POLSEL = DB_ACTV_HIC;
    //EPwm6Regs.DBCTL.bit.IN_MODE = DBA_ALL;
    //EPwm6Regs.DBRED.bit.DBRED = EPWM_DB;
    //EPwm6Regs.DBFED.bit.DBFED = EPWM_DB;
}

// EPWM7 is  unused.
// InitEPwm7Example - Initialize EPWM2 configuration
//
void InitEPwm7Example()
{
    SyncSocRegs.SYNCSELECT.bit.EPWM7SYNCIN = 0;
    EPwm7Regs.TBPRD = 4999;                       // Set timer period
    EPwm7Regs.TBPHS.bit.TBPHS = 0x0000;           // Phase is 0
    EPwm7Regs.TBCTR = 0x0000;                     // Clear counter

    //
    // Setup TBCLK
    //
    EPwm7Regs.TBCTL.bit.CTRMODE = TB_COUNT_DOWN; // Count down
    EPwm7Regs.TBCTL.bit.PHSEN = TB_ENABLE;        // Disable phase loading
    EPwm7Regs.TBCTL.bit.HSPCLKDIV = TB_DIV2;       // Clock ratio to SYSCLKOUT
    EPwm7Regs.TBCTL.bit.CLKDIV = TB_DIV1;
    EPwm7Regs.TBCTL.bit.SYNCOSEL = TB_SYNC_IN;

    EPwm7Regs.CMPCTL.bit.SHDWAMODE = CC_SHADOW;    // Load registers every ZERO
    EPwm7Regs.CMPCTL.bit.SHDWBMODE = CC_SHADOW;
    EPwm7Regs.CMPCTL.bit.LOADAMODE = CC_CTR_ZERO;
    EPwm7Regs.CMPCTL.bit.LOADBMODE = CC_CTR_ZERO;

    //
    // Setup compare
    //
    EPwm7Regs.CMPA.bit.CMPA = 2500;

    //
    // Set actions
    //
    EPwm7Regs.AQCTLA.bit.ZRO = AQ_CLEAR;            // Set PWM1A on Zero
    EPwm7Regs.AQCTLA.bit.CAD = AQ_SET;


    //
    // Active High Complementary
    //
    EPwm7Regs.DBCTL.bit.OUT_MODE = DB_DISABLE;
    //EPwm7Regs.DBCTL.bit.POLSEL = DB_ACTV_HIC;
    //EPwm7Regs.DBCTL.bit.IN_MODE = DBA_ALL;
    //EPwm7Regs.DBRED.bit.DBRED = EPWM_DB;
    //EPwm7Regs.DBFED.bit.DBFED = EPWM_DB;
}



void ConfigureADC(void)
{
    EALLOW;

    //
    //write configurations
    //

    AdcbRegs.ADCCTL2.bit.PRESCALE = 6; //set ADCCLK divider to /4
    AdcSetMode(ADC_ADCB, ADC_RESOLUTION_12BIT, ADC_SIGNALMODE_SINGLE);

    //
    //Set pulse positions to late
    //
    AdcbRegs.ADCCTL1.bit.INTPULSEPOS = 1;

    //
    //power up the ADCs
    //
    AdcbRegs.ADCCTL1.bit.ADCPWDNZ = 1;

    //
    //delay for 1ms to allow ADC time to power up
    //
    DELAY_US(1000);

    EDIS;
}

//
// SetupADCSoftware - Setup ADC channels and acquisition window
//
void SetupADCSoftware(void)
{
    Uint16 acqps;

    //
    // Determine minimum acquisition window (in SYSCLKS) based on resolution
    //
    if(ADC_RESOLUTION_12BIT == AdcbRegs.ADCCTL2.bit.RESOLUTION)
    {
        acqps = 14; //75ns
    }
    else //resolution is 16-bit
    {
        acqps = 63; //320ns
    }

    //
    //Select the channels to convert and end of conversion flag
    //ADCB
    //
    EALLOW;
    AdcbRegs.ADCSOC0CTL.bit.CHSEL = 0;  //SOC0 will convert pin B0
    AdcbRegs.ADCSOC0CTL.bit.ACQPS = acqps; //sample window is acqps +
    AdcbRegs.ADCSOC0CTL.bit.TRIGSEL =9;     //1 SYSCLK cycles

    AdcbRegs.ADCSOC1CTL.bit.CHSEL = 1;  //SOC1 will convert pin B1
    AdcbRegs.ADCSOC1CTL.bit.ACQPS = acqps; //sample window is acqps +
    AdcbRegs.ADCSOC1CTL.bit.TRIGSEL =9;     //1 SYSCLK cycles

    AdcbRegs.ADCSOC2CTL.bit.CHSEL = 2;  //SOC2 will convert pin B2
    AdcbRegs.ADCSOC2CTL.bit.ACQPS = acqps; //sample window is acqps +
    AdcbRegs.ADCSOC2CTL.bit.TRIGSEL =9;     //1 SYSCLK cycles

    AdcbRegs.ADCSOC3CTL.bit.CHSEL = 3;  //SOC3 will convert pin B3
    AdcbRegs.ADCSOC3CTL.bit.ACQPS = acqps; //sample window is acqps +
    AdcbRegs.ADCSOC3CTL.bit.TRIGSEL =9;     //1 SYSCLK cycles

    AdcbRegs.ADCINTSEL1N2.bit.INT2SEL = 3; //end of SOC3 will set INT2 flag
    AdcbRegs.ADCINTSEL1N2.bit.INT2E = 1;   //enable INT2 flag
    AdcbRegs.ADCINTFLGCLR.bit.ADCINT2 = 1; //make sure INT2 flag is cleared
    EDIS;
}
//
// End of file
//

  • Hi Sayandev,

    Can you please try the code below? 

    There was some characters within the white space that don't show. All I did was remove the white space at the beginning of the lines that were causing errors and then tabbing them over. That was able to yield a successful build. 

    //###########################################################################
    //
    // FILE:    epwm_deadband_c28.c
    //
    // TITLE:   Check PWM Dead-Band
    //
    //! \addtogroup cpu01_example_list
    //! <h1> EPWM dead band control (epwm_deadband)</h1>
    //!
    //! During the test, monitor ePWM1, ePWM2, and/or ePWM3 outputs
    //! on a scope.
    //!
    //! - ePWM1A is on GPIO0
    //! - ePWM1B is on GPIO1
    //! - ePWM2A is on GPIO2
    //! - ePWM2B is on GPIO3
    //! - ePWM3A is on GPIO4
    //! - ePWM3B is on GPIO5
    //!
    //! This example configures ePWM1, ePWM2 and ePWM3 for:
    //! - Count up/down
    //! - Deadband
    //!
    //! 3 Examples are included:
    //! - ePWM1: Active low PWMs
    //! - ePWM2: Active low complementary PWMs
    //! - ePWM3: Active high complementary PWMs
    //!
    //! Each ePWM is configured to interrupt on the 3rd zero event.
    //! When this happens the deadband is modified such that
    //! 0 <= DB <= DB_MAX.  That is, the deadband will move up and
    //! down between 0 and the maximum value.
    //!
    //! View the EPWM1A/B, EPWM2A/B and EPWM3A/B waveforms
    //! via an oscilloscope
    //
    //
    //###########################################################################
    // $TI Release: F2837xD Support Library v3.12.00.00 $
    // $Release Date: Fri Feb 12 19:03:23 IST 2021 $
    // $Copyright:
    // Copyright (C) 2013-2021 Texas Instruments Incorporated - http://www.ti.com/
    //
    // Redistribution and use in source and binary forms, with or without 
    // modification, are permitted provided that the following conditions 
    // are met:
    // 
    //   Redistributions of source code must retain the above copyright
    //   notice, this list of conditions and the following disclaimer.
    // 
    //   Redistributions in binary form must reproduce the above copyright
    //   notice, this list of conditions and the following disclaimer in the
    //   documentation and/or other materials provided with the
    //   distribution.
    // 
    //   Neither the name of Texas Instruments Incorporated nor the names of
    //   its contributors may be used to endorse or promote products derived
    //   from this software without specific prior written permission.
    // 
    // THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 
    // "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 
    // LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
    // A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 
    // OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 
    // SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 
    // LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
    // DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
    // THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 
    // (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 
    // OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
    // $
    //###########################################################################
    
    //
    // Included Files
    //
    #include "F28x_Project.h"
    
    
    
    //Defines
    #define D12_BUFFER 20
    #define D_BUFFER 5
    //
    //
    //
    // Globals
    //
    Uint16 Mode_current;
    Uint16 D1;
    Uint16 D2;
    Uint16 D;
    Uint16 D1_adcb1;
    Uint16 D2_adcb2;
    Uint16 D_adcb3;
    Uint16 D1_adcbresult1[D12_BUFFER];
    Uint16 D2_adcbresult2[D12_BUFFER];
    Uint16 D_adcbresult3[D_BUFFER];
    Uint16 indexD12;
    Uint16 indexD;
    
    
    //
    // Function Prototypes
    //Here for simple DAB we will use EPWM1, EPWM2, EPWM4, EPWM5, EPWM6
    
    void InitEPwm1Example(void);
    void InitEPwm2Example(void);
    void InitEPwm3Example(void);
    void InitEPwm4Example(void);
    void InitEPwm5Example(void);
    void InitEPwm6Example(void);
    void InitEPwm7Example(void);
    
    void ConfigureADC(void);
    void SetupADCSoftware(void);
    
    __interrupt void adcb2_isr(void);
    
    
    //
    // Main
    //
    void main(void)
    {
    //
    // Step 1. Initialize System Control:
    // PLL, WatchDog, enable Peripheral Clocks
    // This example function is found in the F2837xD_SysCtrl.c file.
    //
        InitSysCtrl();
    
    //
    // Step 2. Initialize GPIO:
    // This example function is found in the F2837xD_Gpio.c file and
    // illustrates how to set the GPIO to its default state.
    //
        InitGpio();
    
    //
    // enable PWM1, PWM2 and PWM3
    //
        CpuSysRegs.PCLKCR2.bit.EPWM1=1;
        CpuSysRegs.PCLKCR2.bit.EPWM2=1;
        CpuSysRegs.PCLKCR2.bit.EPWM3=1;
        CpuSysRegs.PCLKCR2.bit.EPWM4=1;
        CpuSysRegs.PCLKCR2.bit.EPWM5=1;
        CpuSysRegs.PCLKCR2.bit.EPWM6=1;
        CpuSysRegs.PCLKCR2.bit.EPWM7=1;
    
    //
    // For this case just init GPIO pins for ePWM1, ePWM2, ePWM3
    // These functions are in the F2837xD_EPwm.c file
    //
        InitEPwm1Gpio();
        InitEPwm2Gpio();
        InitEPwm3Gpio();
        InitEPwm4Gpio();
        InitEPwm5Gpio();
        InitEPwm6Gpio();
        InitEPwm7Gpio();
    
    //
    // Step 3. Clear all interrupts and initialize PIE vector table:
    // Disable CPU interrupts
    //
        DINT;
    
    //
    // Initialize the PIE control registers to their default state.
    // The default state is all PIE interrupts disabled and flags
    // are cleared.
    // This function is found in the F2837xD_PieCtrl.c file.
    //
        InitPieCtrl();
    
    //
    // Disable CPU interrupts and clear all CPU interrupt flags:
    //
        IER = 0x0000;
        IFR = 0x0000;
    
    //
    // Initialize the PIE vector table with pointers to the shell Interrupt
    // Service Routines (ISR).
    // This will populate the entire table, even if the interrupt
    // is not used in this example.  This is useful for debug purposes.
    // The shell ISR routines are found in F2837xD_DefaultIsr.c.
    // This function is found in F2837xD_PieVect.c.
    //
        InitPieVectTable();
    
    //
    // Interrupts that are used in this example are re-mapped to
    // ISR functions found within this file.
    //
        EALLOW; // This is needed to write to EALLOW protected registers
        PieVectTable.ADCB2_INT = &adcb2_isr;
        EDIS;   // This is needed to disable write to EALLOW protected registers
    
    //
    // Step 4. Initialize the Device Peripherals:
    //
        EALLOW;
        CpuSysRegs.PCLKCR0.bit.TBCLKSYNC =0;
        EDIS;
    
        InitEPwm1Example();
        InitEPwm2Example();
        InitEPwm3Example();
        InitEPwm4Example();
        InitEPwm5Example();
        InitEPwm6Example();
        InitEPwm7Example();
    
    
    
    //
    // Step 5. User specific code, enable interrupts:
    // Initialize counters:
    //
    
    //
    // Enable CPU INT10 which is connected to ADCB2 INT:
    //
    
        IER |= M_INT10;
    
    //
    // Enable ADCB2 INTn in the PIE: Group 10 interrupt 6
    //
    
        PieCtrlRegs.PIEIER10.bit.INTx6 = 1;
    
    //
    // Enable global Interrupts and higher priority real-time debug events:
    //
        EINT;  // Enable Global interrupt INTM
        ERTM;  // Enable Global realtime interrupt DBGM
    
    
    //
    //
    // Initialize results buffer
    //
        for(indexD12 = 0; indexD12 < D12_BUFFER; indexD12++)
        {
            D1_adcbresult1[indexD12] = 0;
            D2_adcbresult2[indexD12] = 0;
        }
        for(indexD = 0; indexD < D_BUFFER; indexD++)
        {
            D_adcbresult3[indexD] = 0;
        }
         indexD12 = 0;
         indexD   = 0;
         D1_adcb1 = 2500;
         D2_adcb2 = 2500;
         D_adcb3 = 10;
         D1 = 2500;
         D2 = 2500;
         D = 10;
    
    // Setup ADC
    
         ConfigureADC();
         SetupADCSoftware();
    
    //
        //start ePWM
        //
        EPwm3Regs.ETSEL.bit.SOCAEN = 1;  //enable SOCA
        EPwm3Regs.TBCTL.bit.CTRMODE = TB_COUNT_DOWN; //unfreeze, and enter down count mode
    
        EALLOW;
        CpuSysRegs.PCLKCR0.bit.TBCLKSYNC =1;
        EDIS;
    //
    // Step 6. IDLE loop. Just sit and loop forever (optional):
    //
        do
            {
                //
                // Wait while ePWM causes ADC conversions.
                // ADCA1 ISR processes each new set of conversions.
                //
            }
            while(1);
    }
    
    
    //
    // adcb2_isr
    //
    __interrupt void adcb2_isr(void)
     {
         Uint16 i;
         Mode_current  = AdcbResultRegs.ADCRESULT0;
         D1_adcbresult1[indexD12] = AdcbResultRegs.ADCRESULT1;
         D2_adcbresult2[indexD12++] = AdcbResultRegs.ADCRESULT2;
         D_adcbresult3[indexD++] = AdcbResultRegs.ADCRESULT3;
    
         if (indexD12 >= D12_BUFFER)
         {   indexD12 = 0;
             D1_adcb1 = 0;
             D2_adcb2 = 0;
             for(i = 0; i < D12_BUFFER; i++)
             {D1_adcb1 = D1_adcb1 + D1_adcbresult1[i];
              D2_adcb2 = D2_adcb2 + D2_adcbresult2[i];
             }
             D1_adcb1 = D1_adcb1/D12_BUFFER;
             D2_adcb2 = D2_adcb2/D12_BUFFER;
    
             D1 = D1_adcb1 * 0.6297;
             D2 = D2_adcb2 * 0.6297;
         }
    
    
         //Limiter for D1 and D2
        if (D1 < 750)
        {D1 = 750;
        }
        else if (D1 > 2500)
        {D1 = 2500;
        }
    
        if (D2 < 750)
        {D2 = 750;
        }
        else if (D2 > 2500)
        {D2 = 2500;
        }
     //
     //
         if (indexD >= D_BUFFER)
          {  indexD = 0;
             D_adcb3 = 0;
             for(i = 0; i < D_BUFFER; i++)
               {D_adcb3 = D_adcb3 + D_adcbresult3[i];
               }
               D_adcb3 = D_adcb3/D_BUFFER;
    
               D_adcb3  = D_adcb3 * 0.3148;
          }// 0.3148 is the calculated factor required to match the adcin results and TBPHS register
         if (Mode_current > 2024)
         { D = D_adcb3;
         if (D > 1125)
         {D =1125;
         }}
         else
         { D = 4999-D_adcb3;
         if (D < 4249)
         {D =4249;
         }}
    
        EPwm2Regs.TBPHS.bit.TBPHS = D1;
        EPwm4Regs.TBPHS.bit.TBPHS = D;
        EPwm5Regs.TBPHS.bit.TBPHS = D;
        EPwm6Regs.TBPHS.bit.TBPHS = D2;
    
         //
         // Clear INT flag for this timer
         //
             AdcbRegs.ADCINTFLGCLR.bit.ADCINT2 = 1; //clear INT2 flag
         //
         //
    
    
        //
        // Acknowledge this interrupt to receive more interrupts from group 3
        //
        PieCtrlRegs.PIEACK.all = PIEACK_GROUP10;
    }
    
    //
    // InitEPwm1Example - Initialize EPWM1 configuration
    //
    void InitEPwm1Example()
    {
        EPwm1Regs.TBPRD = 4999;                       // Set timer period
        EPwm1Regs.TBPHS.bit.TBPHS = 0x0000;           // Phase is 0
        EPwm1Regs.TBCTR = 0x0000;                     // Clear counter
    
        //
        // Setup TBCLK
        //
        EPwm1Regs.TBCTL.bit.CTRMODE = TB_COUNT_DOWN; // Count down
        EPwm1Regs.TBCTL.bit.PHSEN = TB_DISABLE;        // Disable phase loading
        EPwm1Regs.TBCTL.bit.HSPCLKDIV = TB_DIV2;       // Clock ratio to SYSCLKOUT
        EPwm1Regs.TBCTL.bit.CLKDIV = TB_DIV1;
        EPwm1Regs.TBCTL.bit.SYNCOSEL = TB_CTR_ZERO;
    
        EPwm1Regs.CMPCTL.bit.SHDWAMODE = CC_SHADOW;    // Load registers every ZERO
        EPwm1Regs.CMPCTL.bit.SHDWBMODE = CC_SHADOW;
        EPwm1Regs.CMPCTL.bit.LOADAMODE = CC_CTR_ZERO;
        EPwm1Regs.CMPCTL.bit.LOADBMODE = CC_CTR_ZERO;
    
        //
        // Setup compare
        //
        EPwm1Regs.CMPA.bit.CMPA = 2500;
    
        //
        // Set actions
        //
        EPwm1Regs.AQCTLA.bit.ZRO = AQ_CLEAR;            // Set PWM1A on CMPA and reset at ZRO
        EPwm1Regs.AQCTLA.bit.CAD = AQ_SET;
    
        //
        // Active High Complementary
        //
        EPwm1Regs.DBCTL.bit.OUT_MODE = DB_DISABLE;      // Disable deadband since gate driver have its own
        //EPwm1Regs.DBCTL.bit.POLSEL = DB_ACTV_HIC;
        //EPwm1Regs.DBCTL.bit.IN_MODE = DBA_ALL;
        //EPwm1Regs.DBRED.bit.DBRED = EPWM_DB;
        //EPwm1Regs.DBFED.bit.DBFED = EPWM_DB;
    
    
    }
    
    //
    // InitEPwm2Example - Initialize EPWM2 configuration
    //
    void InitEPwm2Example()
    {
        EPwm2Regs.TBPRD = 4999;                       // Set timer period
        EPwm2Regs.TBPHS.bit.TBPHS = 2500;               // Phase is 0
        EPwm2Regs.TBCTR = 0x0000;                     // Clear counter
    
        //
        // Setup TBCLK
        //
        EPwm2Regs.TBCTL.bit.CTRMODE = TB_COUNT_DOWN; // Count down
        EPwm2Regs.TBCTL.bit.PHSEN = TB_ENABLE;        // Disable phase loading
        EPwm2Regs.TBCTL.bit.HSPCLKDIV = TB_DIV2;       // Clock ratio to SYSCLKOUT
        EPwm2Regs.TBCTL.bit.CLKDIV = TB_DIV1;
        EPwm2Regs.TBCTL.bit.SYNCOSEL = TB_SYNC_IN;
    
        EPwm2Regs.CMPCTL.bit.SHDWAMODE = CC_SHADOW;    // Load registers every ZERO
        EPwm2Regs.CMPCTL.bit.SHDWBMODE = CC_SHADOW;
        EPwm2Regs.CMPCTL.bit.LOADAMODE = CC_CTR_ZERO;
        EPwm2Regs.CMPCTL.bit.LOADBMODE = CC_CTR_ZERO;
    
        //
        // Setup compare
        //
        EPwm2Regs.CMPA.bit.CMPA = 2500;
    
        //
        // Set actions
        //
        EPwm2Regs.AQCTLA.bit.ZRO = AQ_CLEAR;            // Set PWM2A on Zero
        EPwm2Regs.AQCTLA.bit.CAD = AQ_SET;
    
        //
        // Active High Complementary
        //
        EPwm2Regs.DBCTL.bit.OUT_MODE = DB_DISABLE;
        //EPwm2Regs.DBCTL.bit.POLSEL = DB_ACTV_HIC;
        //EPwm2Regs.DBCTL.bit.IN_MODE = DBA_ALL;
        //EPwm2Regs.DBRED.bit.DBRED = EPWM_DB;
        //EPwm2Regs.DBFED.bit.DBFED = EPWM_DB;
    }
    
    // EPWM3 will be unused.
    // InitEPwm3Example - Initialize EPWM2 configuration
    //
    void InitEPwm3Example()
    {
        EPwm3Regs.TBPRD = 4999;                       // Set timer period
        EPwm3Regs.TBPHS.bit.TBPHS = 0x0000;                // Phase is 0
        EPwm3Regs.TBCTR = 0x0000;                     // Clear counter
    
        //
        // Setup TBCLK
        //
        EPwm3Regs.TBCTL.bit.PHSEN = TB_ENABLE;        // Disable phase loading
        EPwm3Regs.TBCTL.bit.HSPCLKDIV = TB_DIV2;       // Clock ratio to SYSCLKOUT
        EPwm3Regs.TBCTL.bit.CLKDIV = TB_DIV1;
        EPwm3Regs.TBCTL.bit.SYNCOSEL = TB_SYNC_IN;
    
        EPwm3Regs.CMPCTL.bit.SHDWAMODE = CC_SHADOW;    // Load registers every ZERO
        EPwm3Regs.CMPCTL.bit.SHDWBMODE = CC_SHADOW;
        EPwm3Regs.CMPCTL.bit.LOADAMODE = CC_CTR_ZERO;
        EPwm3Regs.CMPCTL.bit.LOADBMODE = CC_CTR_ZERO;
    
        //
        // Setup compare
        //
        EPwm3Regs.CMPA.bit.CMPA = 2500;
    
        //
        // Set actions
        //
        EPwm3Regs.AQCTLA.bit.ZRO = AQ_CLEAR;            // Set PWM1A on Zero
        EPwm3Regs.AQCTLA.bit.CAD = AQ_SET;
    
        //
        // Active High Complementary
        //
        EPwm3Regs.DBCTL.bit.OUT_MODE = DB_DISABLE;
        //EPwm3Regs.DBCTL.bit.POLSEL = DB_ACTV_HIC;
        //EPwm3Regs.DBCTL.bit.IN_MODE = DBA_ALL;
        //EPwm3Regs.DBRED.bit.DBRED = EPWM_DB;
        //EPwm3Regs.DBFED.bit.DBFED = EPWM_DB;
    
        //
       // start SOC
       //
        EPwm3Regs.ETSEL.bit.SOCAEN    = 0;    // Disable SOC on A group
        EPwm3Regs.ETSEL.bit.SOCASEL    = 5;   // Select SOC on down-count
        EPwm3Regs.ETPS.bit.SOCAPRD = 1;       // Generate pulse on 1st event
        EPwm3Regs.TBCTL.bit.CTRMODE = TB_FREEZE; // FREEZE
    }
    
    //
    // InitEPwm4Example - Initialize EPWM2 configuration
    //
    void InitEPwm4Example()
    {
        SyncSocRegs.SYNCSELECT.bit.EPWM4SYNCIN = 0;   //EPWM1SYNCOUT
        EPwm4Regs.TBPRD = 4999;                       // Set timer period
        EPwm4Regs.TBPHS.bit.TBPHS = 0;           // Phase is D
        EPwm4Regs.TBCTR = 0x0000;                     // Clear counter
    
        //
        // Setup TBCLK
        //
        EPwm4Regs.TBCTL.bit.CTRMODE = TB_COUNT_DOWN; // Count down
        EPwm4Regs.TBCTL.bit.PHSEN = TB_ENABLE;        // Disable phase loading
        EPwm4Regs.TBCTL.bit.HSPCLKDIV = TB_DIV2;       // Clock ratio to SYSCLKOUT
        EPwm4Regs.TBCTL.bit.CLKDIV = TB_DIV1;
        EPwm4Regs.TBCTL.bit.SYNCOSEL = TB_SYNC_IN;   //It should be set to zero
    
        EPwm4Regs.CMPCTL.bit.SHDWAMODE = CC_SHADOW;    // Load registers every ZERO
        EPwm4Regs.CMPCTL.bit.SHDWBMODE = CC_SHADOW;
        EPwm4Regs.CMPCTL.bit.LOADAMODE = CC_CTR_ZERO;
        EPwm4Regs.CMPCTL.bit.LOADBMODE = CC_CTR_ZERO;
    
        //
        // Setup compare
        //
        EPwm4Regs.CMPA.bit.CMPA = 2500;
    
        //
        // Set actions
        //
        EPwm4Regs.AQCTLA.bit.ZRO = AQ_CLEAR;            // Set PWM4A on Zero
        EPwm4Regs.AQCTLA.bit.CAD = AQ_SET;
    
    
        //
        // Active High Complementary
        //
        EPwm4Regs.DBCTL.bit.OUT_MODE = DB_DISABLE;
        //EPwm4Regs.DBCTL.bit.POLSEL = DB_ACTV_HIC;
        //EPwm4Regs.DBCTL.bit.IN_MODE = DBA_ALL;
        //EPwm4Regs.DBRED.bit.DBRED = EPWM_DB;
        //EPwm4Regs.DBFED.bit.DBFED = EPWM_DB;
    }
    
    //
    // InitEPwm5Example - Initialize EPWM2 configuration
    //
    void InitEPwm5Example()
    {
        EPwm5Regs.TBPRD = 4999;                       // Set timer period
        EPwm5Regs.TBPHS.bit.TBPHS = 0;               // Phase is D
        EPwm5Regs.TBCTR = 0x0000;                     // Clear counter
    
        //
        // Setup TBCLK
        //
        EPwm5Regs.TBCTL.bit.CTRMODE = TB_COUNT_DOWN;  // Count down
        EPwm5Regs.TBCTL.bit.PHSEN = TB_ENABLE;        // Disable phase loading
        EPwm5Regs.TBCTL.bit.HSPCLKDIV = TB_DIV2;       // Clock ratio to SYSCLKOUT
        EPwm5Regs.TBCTL.bit.CLKDIV = TB_DIV1;
        EPwm5Regs.TBCTL.bit.SYNCOSEL = TB_CTR_ZERO;
    
        EPwm5Regs.CMPCTL.bit.SHDWAMODE = CC_SHADOW;    // Load registers every ZERO
        EPwm5Regs.CMPCTL.bit.SHDWBMODE = CC_SHADOW;
        EPwm5Regs.CMPCTL.bit.LOADAMODE = CC_CTR_ZERO;
        EPwm5Regs.CMPCTL.bit.LOADBMODE = CC_CTR_ZERO;
    
        //
        // Setup compare
        //
        EPwm5Regs.CMPA.bit.CMPA = 2500;
    
        //
        // Set actions
        //
        EPwm5Regs.AQCTLA.bit.ZRO = AQ_CLEAR;            // Set PWM1A on Zero
        EPwm5Regs.AQCTLA.bit.CAD = AQ_SET;
    
        //
        // Active High Complementary
        //
        EPwm5Regs.DBCTL.bit.OUT_MODE = DB_DISABLE;
        //EPwm5Regs.DBCTL.bit.POLSEL = DB_ACTV_HIC;
        //EPwm5Regs.DBCTL.bit.IN_MODE = DBA_ALL;
        //EPwm5Regs.DBRED.bit.DBRED = EPWM_DB;
        //EPwm5Regs.DBFED.bit.DBFED = EPWM_DB;
    }
    
    //
    // InitEPwm6Example - Initialize EPWM2 configuration
    //
    void InitEPwm6Example()
    {
        EPwm6Regs.TBPRD = 4999;                       // Set timer period
        EPwm6Regs.TBPHS.bit.TBPHS = 0;           // Phase is 0
        EPwm6Regs.TBCTR = 0x0000;                     // Clear counter
    
        //
        // Setup TBCLK
        //
        EPwm6Regs.TBCTL.bit.CTRMODE = TB_COUNT_DOWN; // Count down
        EPwm6Regs.TBCTL.bit.PHSEN = TB_ENABLE;        // Disable phase loading
        EPwm6Regs.TBCTL.bit.HSPCLKDIV = TB_DIV2;       // Clock ratio to SYSCLKOUT
        EPwm6Regs.TBCTL.bit.CLKDIV = TB_DIV1;
        EPwm6Regs.TBCTL.bit.SYNCOSEL = TB_SYNC_IN;
    
        EPwm6Regs.CMPCTL.bit.SHDWAMODE = CC_SHADOW;    // Load registers every ZERO
        EPwm6Regs.CMPCTL.bit.SHDWBMODE = CC_SHADOW;
        EPwm6Regs.CMPCTL.bit.LOADAMODE = CC_CTR_ZERO;
        EPwm6Regs.CMPCTL.bit.LOADBMODE = CC_CTR_ZERO;
    
        //
        // Setup compare
        //
        EPwm6Regs.CMPA.bit.CMPA = 2500;
    
        //
        // Set actions
        //
        EPwm6Regs.AQCTLA.bit.ZRO = AQ_CLEAR;            // Set PWM6A on Zero
        EPwm6Regs.AQCTLA.bit.CAD = AQ_SET;
    
        //
        // Active High Complementary
        //
        EPwm6Regs.DBCTL.bit.OUT_MODE = DB_FULL_ENABLE;
        //EPwm6Regs.DBCTL.bit.POLSEL = DB_ACTV_HIC;
        //EPwm6Regs.DBCTL.bit.IN_MODE = DBA_ALL;
        //EPwm6Regs.DBRED.bit.DBRED = EPWM_DB;
        //EPwm6Regs.DBFED.bit.DBFED = EPWM_DB;
    }
    
    // EPWM7 is  unused.
    // InitEPwm7Example - Initialize EPWM2 configuration
    //
    void InitEPwm7Example()
    {
        SyncSocRegs.SYNCSELECT.bit.EPWM7SYNCIN = 0;
        EPwm7Regs.TBPRD = 4999;                       // Set timer period
        EPwm7Regs.TBPHS.bit.TBPHS = 0x0000;           // Phase is 0
        EPwm7Regs.TBCTR = 0x0000;                     // Clear counter
    
        //
        // Setup TBCLK
        //
        EPwm7Regs.TBCTL.bit.CTRMODE = TB_COUNT_DOWN; // Count down
        EPwm7Regs.TBCTL.bit.PHSEN = TB_ENABLE;        // Disable phase loading
        EPwm7Regs.TBCTL.bit.HSPCLKDIV = TB_DIV2;       // Clock ratio to SYSCLKOUT
        EPwm7Regs.TBCTL.bit.CLKDIV = TB_DIV1;
        EPwm7Regs.TBCTL.bit.SYNCOSEL = TB_SYNC_IN;
    
        EPwm7Regs.CMPCTL.bit.SHDWAMODE = CC_SHADOW;    // Load registers every ZERO
        EPwm7Regs.CMPCTL.bit.SHDWBMODE = CC_SHADOW;
        EPwm7Regs.CMPCTL.bit.LOADAMODE = CC_CTR_ZERO;
        EPwm7Regs.CMPCTL.bit.LOADBMODE = CC_CTR_ZERO;
    
        //
        // Setup compare
        //
        EPwm7Regs.CMPA.bit.CMPA = 2500;
    
        //
        // Set actions
        //
        EPwm7Regs.AQCTLA.bit.ZRO = AQ_CLEAR;            // Set PWM1A on Zero
        EPwm7Regs.AQCTLA.bit.CAD = AQ_SET;
    
    
        //
        // Active High Complementary
        //
        EPwm7Regs.DBCTL.bit.OUT_MODE = DB_DISABLE;
        //EPwm7Regs.DBCTL.bit.POLSEL = DB_ACTV_HIC;
        //EPwm7Regs.DBCTL.bit.IN_MODE = DBA_ALL;
        //EPwm7Regs.DBRED.bit.DBRED = EPWM_DB;
        //EPwm7Regs.DBFED.bit.DBFED = EPWM_DB;
    }
    
    
    
    void ConfigureADC(void)
    {
        EALLOW;
    
        //
        //write configurations
        //
    
        AdcbRegs.ADCCTL2.bit.PRESCALE = 6; //set ADCCLK divider to /4
        AdcSetMode(ADC_ADCB, ADC_RESOLUTION_12BIT, ADC_SIGNALMODE_SINGLE);
    
        //
        //Set pulse positions to late
        //
        AdcbRegs.ADCCTL1.bit.INTPULSEPOS = 1;
    
        //
        //power up the ADCs
        //
        AdcbRegs.ADCCTL1.bit.ADCPWDNZ = 1;
    
        //
        //delay for 1ms to allow ADC time to power up
        //
        DELAY_US(1000);
    
        EDIS;
    }
    
    //
    // SetupADCSoftware - Setup ADC channels and acquisition window
    //
    void SetupADCSoftware(void)
    {
        Uint16 acqps;
    
        //
        // Determine minimum acquisition window (in SYSCLKS) based on resolution
        //
        if(ADC_RESOLUTION_12BIT == AdcbRegs.ADCCTL2.bit.RESOLUTION)
        {
            acqps = 14; //75ns
        }
        else //resolution is 16-bit
        {
            acqps = 63; //320ns
        }
    
        //
        //Select the channels to convert and end of conversion flag
        //ADCB
        //
        EALLOW;
        AdcbRegs.ADCSOC0CTL.bit.CHSEL = 0;  //SOC0 will convert pin B0
        AdcbRegs.ADCSOC0CTL.bit.ACQPS = acqps; //sample window is acqps +
        AdcbRegs.ADCSOC0CTL.bit.TRIGSEL =9;     //1 SYSCLK cycles
    
        AdcbRegs.ADCSOC1CTL.bit.CHSEL = 1;  //SOC1 will convert pin B1
        AdcbRegs.ADCSOC1CTL.bit.ACQPS = acqps; //sample window is acqps +
        AdcbRegs.ADCSOC1CTL.bit.TRIGSEL =9;     //1 SYSCLK cycles
    
        AdcbRegs.ADCSOC2CTL.bit.CHSEL = 2;  //SOC2 will convert pin B2
        AdcbRegs.ADCSOC2CTL.bit.ACQPS = acqps; //sample window is acqps +
        AdcbRegs.ADCSOC2CTL.bit.TRIGSEL =9;     //1 SYSCLK cycles
    
        AdcbRegs.ADCSOC3CTL.bit.CHSEL = 3;  //SOC3 will convert pin B3
        AdcbRegs.ADCSOC3CTL.bit.ACQPS = acqps; //sample window is acqps +
        AdcbRegs.ADCSOC3CTL.bit.TRIGSEL =9;     //1 SYSCLK cycles
    
        AdcbRegs.ADCINTSEL1N2.bit.INT2SEL = 3; //end of SOC3 will set INT2 flag
        AdcbRegs.ADCINTSEL1N2.bit.INT2E = 1;   //enable INT2 flag
        AdcbRegs.ADCINTFLGCLR.bit.ADCINT2 = 1; //make sure INT2 flag is cleared
        EDIS;
    }
    //
    // End of file
    //

    Best Regards,

    Marlyn

  • There was some characters within the white space that don't show.

    How to debug this hidden characters?

  • Thanks a ton Marlyn for saving me. I would just like to ask another question. Can you please tell me how to the code runs for this particular line?

    " D_adcbresult3[indexD++] = AdcbResultRegs.ADCRESULT3;"

    My understanding is : 

    D_adcresults3(indexD) = AdcbResultRegs.ADCRESULT3;

    indexD = indexD+1;

    ....passed to next line of code..

    Am I right?

  • Hi Sayandev,

    Yes, your understanding is correct. If you open up an 'Expression Window' within CCS you'll be able to see the value of indexD incrementing one by one and the corresponding element of D_adcbresult3 populated with the ADC conversion result.

    Best Regards,

    Marlyn

  • Hi Sayandev,

    For the hidden character, the way I was able to detect it is that the lines of code gave an error even if they were commented out. Removing the white space to the left of the lines of code fixed the issue so I think there was something incorrect about the return character for each new line of code. 

    Best Regards,

    Marlyn