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Part Number: TMS320F28379D
Other Parts Discussed in Thread: C2000WARE
Hi,
does anyone know what could caused the below warnings:
* Build-variable'F2837xD_header' canot be resolved. This project may not be build as expected
*Build-variable'Lab_common' cannot be resolved. This project may not be build as expected
thankyou
I am building a modified example of the C2000ware lab#6
I am trying configure each module (ADCA,ADCB,ADCC) to generate three ADC interrupt each.
/**********************************************************************
* File: Adc.c -- Solution File
* Devices: TMS320F28x7x
* Author: C2000 Technical Training, Texas Instruments
**********************************************************************/
#include "Lab.h" // Main include file
uint16_t adcAResult0; //mz2-26-2020
uint16_t adcAResult1;
uint16_t adcAResult2;
/**********************************************************************
* Function: InitAdca&b()
*
* Description: Initializes ADC-A & B on the F28x7x
**********************************************************************/
void InitAdca(void)
{
asm(" EALLOW"); // Enable EALLOW protected register access
//--- Reset the ADC. This is good programming practice.
DevCfgRegs.SOFTPRES13.bit.ADC_A = 1; // ADC is reset
DevCfgRegs.SOFTPRES13.bit.ADC_A = 0; // ADC is released from reset
//--- Configure the ADC base registers
AdcaRegs.ADCCTL1.all = 0x0004; // Main ADC configuration
// bit 15-14 00: reserved
// bit 13 0: ADCBSY, ADC busy, Read-only
// bit 12 0: reserved
// bit 11-8 000: ADCBSYCHN, ADC busy channel, Read-only
// bit 7 0: ADCPWDNZ, ADC power down, 0 = powered down, 1 = powered up
// bit 6-3 0000: reserved
// bit 2 1: INTPULSEPOS, INT pulse generation, 0 = SOC, 1 = EOC
// bit 1-0 00: reserved
AdcaRegs.ADCCTL2.all = 0x0006; // ADC clock configuration
// bit 15-8 0's: reserved
// bit 7 0: SIGNALMODE, configured by AdcSetMode()
// below to get calibration correct
// bit 6 0: RESOLUTION, configured by AdcSetMode()
// below to get calibration correct
// bit 5-4 00: reserved
// bit 3-0 0110: PRESCALE, ADC clock prescaler. 0110=CPUCLK/4
AdcaRegs.ADCBURSTCTL.all = 0x0000;
// bit 15 0: BURSTEN, 0=burst mode disabled, 1=burst mode enabled
// bit 14-12 000: reserved
// bit 11-8 0000: BURSTSIZE, 0=1 SOC converted (don't care)
// bit 7-6 00: reserved
// bit 5-0 000000: BURSTTRIGSEL, 00=software only (don't care)
AdcaRegs.ADCCTL1.bit.INTPULSEPOS = 1; //mz***2-11-2020
//1 Interrupt pulse generation occurs at the end of the conversion, 1
//cycle prior to the ADC result latching into its result register
//--- Call AdcSetMode() to configure the resolution and signal mode.
// This also performs the correct ADC calibration for the configured mode.
AdcSetMode(ADC_ADCA, ADC_RESOLUTION_12BIT, ADC_SIGNALMODE_SINGLE);
//*******************************Launchpad AA0 pin#30*******************MZ: there is no ADCA0, ADCB0,...in the pie table listing the ADC interrupt. i do think we can use this to generate an interrupt
//--- SOC0 configuration
AdcaRegs.ADCSOC0CTL.bit.TRIGSEL = 7; // Trigger using ePWM2-ADCSOCA (TECH DO PAGE 1324)
AdcaRegs.ADCSOC0CTL.bit.CHSEL = 0; // using soc0 to convert ch 0. in single ended conversion chanel 0 requires the use of ADCINA0 as input(page1271 and1250). Convert channel ADCINA0 (Ch. 0) (TECH DOC. PAGE 1271)
AdcaRegs.ADCSOC0CTL.bit.ACQPS = 19; // Acquisition window set to (19+1)=20 cycles (100 ns with 200 MHz SYSCLK)
AdcaRegs.ADCINTSOCSEL1.bit.SOC0 = 0; // No ADC interrupt triggers SOC0 (TRIGSEL field determines trigger)**MZ; i do not want the interrupt generated by another ADC to trigger soc0
AdcaRegs.ADCSOCPRICTL.bit.SOCPRIORITY = 0; // All SOCs handled in round-robin mode
//--- ADCA0 interrupt configuration uses ADCa Interrupt 1 and 2 Selection Register
AdcaRegs.ADCINTSEL1N2.bit.INT1CONT = 1; // Interrupt pulses regardless of flag state , countinous mode
AdcaRegs.ADCINTSEL1N2.bit.INT1E = 1; // Enable the interrupt in the ADC
AdcaRegs.ADCINTSEL1N2.bit.INT1SEL = 0; // =0h, EOC0 is trigger for ADCINT1 (end of conversion of chanel 0 trigger ADCINT1)
PieCtrlRegs.PIEIER1.bit.INTx1 = 1; // Enable ADCA1 interrupt in PIE group 1
IER |= 0x0001; // Enable INT1 in IER to enable PIE group1
AdcaRegs.ADCCTL1.bit.INTPULSEPOS = 1; //mz***2-11-2020
//EINT; // Enable Global Interrupt
// ******MZ****************************Launchpad AA1 pin#70************************************************
// SOC1 configuration:use of SOC1 to trigger conversion on ADCINA1
AdcaRegs.ADCSOC1CTL.bit.TRIGSEL = 7; //AA1, correspond to ADCINA1 FROM LAUNCHPAD DOC. use soc1. Each SOC is a configuration set defining the single conversion of a single channel. (PAGE1269)
AdcaRegs.ADCSOC1CTL.bit.CHSEL = 1; // AA1 use ch1. using soc1 to convert ch 1. in single ended conversion chanel 1 requires the use of ADCIN1 as input(page1271)
AdcaRegs.ADCSOC1CTL.bit.ACQPS = 300;
//AdcaResult1 = AdcaResultRegs.ADCRESULT1;
AdcaRegs.ADCINTSOCSEL1.bit.SOC1 = 0; // No ADCa interrupt triggers SOC1 (TRIGSEL field determines trigger)**MZ; i do not want the interrupt generated by another ADC to trigger soc1
//- ****ADCA2 interrupt configuration, uses ADC Interrupt 1 and 2 Selection Register
AdcaRegs.ADCINTSEL1N2.bit.INT2CONT = 1; // Interrupt pulses regardless of flag state
AdcaRegs.ADCINTSEL1N2.bit.INT2E = 1; // Enable the interrupt in the ADC
AdcaRegs.ADCINTSEL1N2.bit.INT2SEL = 1; //=1h, EOC1 is trigger for ADCINT2 ( at end of conversion of Ch 1 trigger the ADCINT2 interrupt)
PieCtrlRegs.PIEIER10.bit.INTx2 = 1; // Enable ADCA2 interrupt in PIE group 10
IER |= 0x0010;
AdcaRegs.ADCCTL1.bit.INTPULSEPOS = 1; //mz***2-11-2020
// EINT;
//**************************************Launchpad AA2 pin#29************************************************
// SOC2 configuration:use of SOC2 to trigger conversion on ADCINA2
AdcaRegs.ADCSOC2CTL.bit.TRIGSEL = 7; //AA2 correspond to ADCINA2(ch2), need to use soc2.Each SOC is a configuration set defining the single conversion of a single channel. (PAGE1269)
AdcaRegs.ADCSOC2CTL.bit.CHSEL = 2; //CH2 FOR ADCIN2 (TECH DOC. PAGE 1271)
AdcaRegs.ADCSOC2CTL.bit.ACQPS = 500;
// AdcaResult2 = AdcaResultRegs.ADCRESULT2;
AdcaRegs.ADCINTSOCSEL1.bit.SOC2 = 0; // No ADC interrupt triggers SOC2 (TRIGSEL field determines trigger); i do not want the interrupt generated by another ADC to trigger soc2
//- ********ADCA3 interrupt configuration, uses ADCa Interrupt 3 and 4 Selection Register
AdcaRegs.ADCINTSEL3N4.bit.INT3CONT = 1; // Interrupt pulses regardless of flag state
AdcaRegs.ADCINTSEL3N4.bit.INT3E = 1; // Enable the interrupt in the ADC
AdcaRegs.ADCINTSEL3N4.bit.INT3SEL = 2; //=2h, EOC2 is trigger for ADCINT3( at end of conversion of Ch 2 trigger the interrupt)
PieCtrlRegs.PIEIER10.bit.INTx3 = 1; // Enable ADCA3 interrupt in PIE group 10
IER |= 0x0010;
AdcaRegs.ADCCTL1.bit.INTPULSEPOS = 1; //mz***2-11-2020
//EINT;
//****************************************adca power up & priority*********************************************
AdcaRegs.ADCSOCPRICTL.bit.SOCPRIORITY = 0; // All SOCs handled in round-robin mode
//--- Finish up
AdcaRegs.ADCCTL1.bit.ADCPWDNZ = 1; // Power up the ADC
DelayUs(1000); // Wait 1 ms after power-up before using the ADC
asm(" EDIS"); // Disable EALLOW protected register access
} // end InitAdc()
//******************************************************************************************************************************
void InitAdcb(void)
{
asm(" EALLOW"); // Enable EALLOW protected register access
// Reset the ADC. This is good programming practice.
DevCfgRegs.SOFTPRES13.bit.ADC_B = 1; // ADC is reset
DevCfgRegs.SOFTPRES13.bit.ADC_B = 0; // ADC is released from reset
//--- Configure the ADC base registers
AdcbRegs.ADCCTL1.all = 0x0004; //****mz
// bit 15-14 00: reserved
// bit 13 0: ADCBSY, ADC busy, read-only
// bit 12 0: reserved
// bit 11-8 0's: ADCBSYCHN, ADC busy channel, read-only
// bit 7 0: ADCPWDNZ, ADC power down, 0=powered down, 1=powered up
// bit 6-3 0000: reserved
// bit 2 1: INTPULSEPOS, INT pulse generation, 0=start of conversion, 1=end of conversion
// bit 1-0 00: reserved
AdcbRegs.ADCCTL2.all = 0x0006; // ***mz
// bit 15-8 0's: reserved
// bit 7 0: SIGNALMODE, configured by AdcSetMode() below to get calibration correct
// bit 6 0: RESOLUTION, configured by AdcSetMode() below to get calibration correct
// bit 5-4 00: reserved
// bit 3-0 0110: PRESCALE, ADC clock prescaler. 0110=CPUCLK/4
AdcbRegs.ADCBURSTCTL.all = 0x0000; //***mz
AdcbRegs.ADCCTL1.bit.INTPULSEPOS = 1; //*******mz2-11-2021
//--- Call AdcSetMode() to configure the resolution and signal mode.
// This also performs the correct ADC calibration for the configured mode.
AdcSetMode(ADC_ADCB, ADC_RESOLUTION_12BIT, ADC_SIGNALMODE_SINGLE); //***mz
//******************************************Launchpad AB2 pin#28************************************************************************
//SOC0 configuration ADCB, uses ADCb Interrupt 1 and 2 Selection Register
AdcbRegs.ADCSOC0CTL.bit.TRIGSEL = 7; //AB2, correspond to ADCINB2 FROM LANCHPAD DOC
AdcbRegs.ADCSOC0CTL.bit.CHSEL = 2; // MZ***:used ch 2 (ADCINB2)of B port because it is what i have available in the lunch pad SOC0 will convert ADCINB2
AdcbRegs.ADCSOC0CTL.bit.ACQPS = 19;
AdcbRegs.ADCINTSOCSEL1.bit.SOC2 = 0; //i do not want the interrupt generated by another ADC to trigger soc2
// ADCB1 interrupt configuration, uses ADC Interrupt 1 and 2 Selection Register
AdcbRegs.ADCINTSEL1N2.bit.INT1CONT = 1; //count. mode enable,=1 ADCINT1 pulses generated whenever an EOC pulse is generated
AdcbRegs.ADCINTSEL1N2.bit.INT1E = 1; //=1 ADCINT1 is enabled
AdcbRegs.ADCINTSEL1N2.bit.INT1SEL = 0; //=0h, EOC0 is trigger for ADCINT1
AdcbRegs.ADCSOCPRICTL.bit.SOCPRIORITY = 0;
PieCtrlRegs.PIEIER1.bit.INTx2 = 1; // Enable ADCB1 interrupt in PIE group 1
IER |= 0x0001; // Enable INT1 in IER to enable PIE group1
AdcbRegs.ADCCTL1.bit.INTPULSEPOS = 1; //mz***2-11-2020
// EINT;
//********************************************Launchpad AB3 pin#25 in J3********************************************************************************
//SOC1 configuration ADCB;
AdcbRegs.ADCSOC1CTL.bit.TRIGSEL = 7; //AB3, correspond to ADCINB3 IN LAUNCHPAD, USE SOC3 (TECH DOC. PAGE 1271)
AdcbRegs.ADCSOC1CTL.bit.CHSEL = 3; // CH3 FOR ADCIN3 (TECH DOC. PAGE 1271)
AdcbRegs.ADCSOC1CTL.bit.ACQPS = 300;
AdcbRegs.ADCINTSOCSEL1.bit.SOC3 = 0;
// ADCB1 interrupt configuration, uses ADCb Interrupt 1 and 2 Selection Register
AdcbRegs.ADCINTSEL1N2.bit.INT2CONT = 1;
AdcbRegs.ADCINTSEL1N2.bit.INT2E = 1;
AdcbRegs.ADCINTSEL1N2.bit.INT2SEL = 1; //=1h, EOC1 is trigger for ADCINT2
PieCtrlRegs.PIEIER10.bit.INTx6 = 1; // Enable ADCB2 interrupt in PIE group 10
IER |= 0x0010; // Enable INT1 in IER to enable PIE group10
// EINT;
//********************************************Launchpad AB4 pin#68 inJ7********************************************************************************
//****MZ**SOC1 configuration ADCB;
AdcbRegs.ADCSOC2CTL.bit.TRIGSEL = 7; //AB4, correspond to ADCINB4 IN LAUNCHPAD, USE SOC4 (TECH DOC. PAGE 1271)
AdcbRegs.ADCSOC2CTL.bit.CHSEL = 4; // MZ***:used ch 4 (ADCINB4)of B port
AdcbRegs.ADCSOC2CTL.bit.ACQPS = 500;
AdcbRegs.ADCINTSOCSEL1.bit.SOC4 = 0;
//---***MZ** ADCB1 interrupt configuration, uses ADCb Interrupt 1 and 2 Selection Register
AdcbRegs.ADCINTSEL3N4.bit.INT3CONT = 1;
AdcbRegs.ADCINTSEL3N4.bit.INT3E = 1;
AdcbRegs.ADCINTSEL3N4.bit.INT3SEL = 4; //=4h, EOC4 is trigger for ADCINT3
PieCtrlRegs.PIEIER10.bit.INTx7 = 1; // Enable ADCB3 interrupt in PIE group 10, adcintB3 requires use of ADCINB3 ch AS INPUT which mean use ch#3 of ADCB Module (page1250)
IER |= 0x0010; // Enable INT1 in IER to enable PIE group10
// EINT;
//************************************************adcb power up & priority**************************************************************************************************
AdcbRegs.ADCSOCPRICTL.bit.SOCPRIORITY = 0;
// Finish up FOR ADCB
AdcbRegs.ADCCTL1.bit.ADCPWDNZ = 1;
DelayUs(1000);
asm(" EDIS");
}
//*********************************************************************************************************************************
void InitAdcc(void)
{
asm(" EALLOW"); // Enable EALLOW protected register access
//--- Reset the ADC. This is good programming practice.
DevCfgRegs.SOFTPRES13.bit.ADC_C = 1; // ADC is reset
DevCfgRegs.SOFTPRES13.bit.ADC_C = 0; // ADC is released from reset
//--- Configure the ADC base registers
AdccRegs.ADCCTL1.all = 0x0004; // Main ADC configuration
AdccRegs.ADCCTL2.all = 0x0006; // ADC clock configuration
AdccRegs.ADCBURSTCTL.all = 0x0000;
AdccRegs.ADCCTL1.bit.INTPULSEPOS = 1; //***mz-2/11/2021
//--- Call AdcSetMode() to configure the resolution and signal mode.
// This also performs the correct ADC calibration for the configured mode.
AdcSetMode(ADC_ADCC, ADC_RESOLUTION_12BIT, ADC_SIGNALMODE_SINGLE);
//*******************************Launchpad AC2 pin#27 in J3**********************************************
//--- SOC0 configuration
AdccRegs.ADCSOC0CTL.bit.TRIGSEL = 7; // Trigger using ePWM2-ADCSOCA, SOC2 BECAUSE AC2 (ADCINC2 IN LAUNCHPAD) Each SOC is a configuration set defining the single conversion of a single channel.PAGE1269
AdccRegs.ADCSOC0CTL.bit.CHSEL = 2; // Convert channel ADCINAC2 (Ch. 2)
AdccRegs.ADCSOC0CTL.bit.ACQPS = 19; // Acquisition window set to (19+1)=20 cycles (100 ns with 200 MHz SYSCLK)
AdccRegs.ADCINTSOCSEL1.bit.SOC2 = 0; // No ADC interrupt triggers SOC2 (TRIGSEL field determines trigger)**MZ; i do not want the interrupt generated by another ADC to trigger soc0
//--- ADCc1 interrupt configuration uses ADCC Interrupt 1 and 2 Selection Register
AdccRegs.ADCINTSEL1N2.bit.INT1CONT = 1; // Interrupt pulses regardless of flag state , countinous mode
AdccRegs.ADCINTSEL1N2.bit.INT1E = 1; // Enable the interrupt in the ADC
AdccRegs.ADCINTSEL1N2.bit.INT1SEL = 2; // =2h, EOC2 is trigger for ADCCINT1 (end of conversion of chanel 2 trigger ADCINT1)
PieCtrlRegs.PIEIER1.bit.INTx3 = 1; // Enable ADCC1 interrupt in PIE group 1
IER |= 0x0001; // Enable INT1 in IER to enable PIE group
// EINT; // Enable Global Interrupts
//*********************************Launchpad AC3 pin#24 in J3***************************************************************************
//--- SOC0 configuration
AdccRegs.ADCSOC1CTL.bit.TRIGSEL = 7; // Trigger using ePWM2-ADCSOCA
AdccRegs.ADCSOC1CTL.bit.CHSEL = 3; // Convert channel ADCINAC3 (Ch. 3)
AdccRegs.ADCSOC1CTL.bit.ACQPS = 300; // Acquisition window set to (19+1)=20 cycles (100 ns with 200 MHz SYSCLK)
AdccRegs.ADCINTSOCSEL1.bit.SOC3 = 0; // No ADC interrupt triggers SOC3 (TRIGSEL field determines trigger)**MZ; i do not want the interrupt generated by another ADC to trigger soc0
//--- ADCc2 interrupt configuration uses ADCC Interrupt 1 and 2 Selection Register
AdccRegs.ADCINTSEL1N2.bit.INT2CONT = 1; // Interrupt pulses regardless of flag state , countinous mode
AdccRegs.ADCINTSEL1N2.bit.INT2E = 1; // Enable the interrupt in the ADC
AdccRegs.ADCINTSEL1N2.bit.INT2SEL = 3; // =3h, EOC3 is trigger for ADCCINT2 (end of conversion of chanel 3 trigger ADCINT2)
PieCtrlRegs.PIEIER10.bit.INTx10 = 1; // Enable ADCC2 interrupt in PIE group 10
IER |= 0x0010; // Enable INT1 in IER to enable PIE group10
//EINT; // Enable Global Interrupts
// ****************************Launchpad AC4 pin#67 in J7***************************************************************************
//--- SOC1 configuration
AdccRegs.ADCSOC2CTL.bit.TRIGSEL = 7; // Trigger using ePWM2-ADCSOCA
AdccRegs.ADCSOC2CTL.bit.CHSEL = 3; // Convert channel ADCINAC4 (Ch. 4)
AdccRegs.ADCSOC2CTL.bit.ACQPS = 500; // Acquisition window set to (19+1)=20 cycles (100 ns with 200 MHz SYSCLK)
AdccRegs.ADCINTSOCSEL1.bit.SOC4 = 0; // No ADC interrupt triggers SOC4 (TRIGSEL field determines trigger)**MZ; i do not want the interrupt generated by another ADC to trigger soc0
//--- ADCc3 interrupt configuration uses ADCC Interrupt 3 and 4 Selection Register
AdccRegs.ADCINTSEL3N4.bit.INT3CONT = 1; // Interrupt pulses regardless of flag state , countinous mode
AdccRegs.ADCINTSEL3N4.bit.INT3E = 1; // Enable the interrupt in the ADC
AdccRegs.ADCINTSEL3N4.bit.INT3SEL = 3; // =3h, EOC3 is trigger for ADCINT2 (end of conversion of chanel 3 trigger ADCINT2)
PieCtrlRegs.PIEIER10.bit.INTx11 = 1; // Enable ADCC3 interrupt in PIE group 10
IER |= 0x0010; // Enable INT1 in IER to enable PIE group10
//EINT; // Enable Global Interrupts
// ****************************Launchpad AC5 pin#64 in J7***************************************************************************
//--- SOC2 configuration
AdccRegs.ADCSOC4CTL.bit.TRIGSEL = 7; // Trigger using ePWM2-ADCSOCA
AdccRegs.ADCSOC4CTL.bit.CHSEL = 4; // Convert channel ADCINAC5 (Ch. 5)
AdccRegs.ADCSOC4CTL.bit.ACQPS = 400; // Acquisition window set to (19+1)=20 cycles (100 ns with 200 MHz SYSCLK)
AdccRegs.ADCINTSOCSEL1.bit.SOC5 = 0; // No ADC interrupt triggers SOC3 (TRIGSEL field determines trigger)**MZ; i do not want the interrupt generated by another ADC to trigger soc0
//--- ADCc4 interrupt configuration uses ADCC Interrupt 3 and 4 Selection Register
AdccRegs.ADCINTSEL3N4.bit.INT4CONT = 1; // Interrupt pulses regardless of flag state , countinous mode
AdccRegs.ADCINTSEL3N4.bit.INT4E = 1; // Enable the 3RD interrupt in the ADC
AdccRegs.ADCINTSEL3N4.bit.INT4SEL = 4; // =4h, EOC4 is trigger for ADCINT4 (end of conversion of chanel 4 trigger ADCINT3)
PieCtrlRegs.PIEIER10.bit.INTx12 = 1; // Enable ADCC4 interrupt in PIE group 10
IER |= 0x0010; // Enable INT1 in IER to enable PIE group10
// EINT; // Enable Global Interrupts
// end InitAdc()
//--- end of file -----------------------------------------------------
// ************************************************adcc power up & priority**************************************************************************************************
AdccRegs.ADCSOCPRICTL.bit.SOCPRIORITY = 0;
// Finish up FOR ADCC
AdccRegs.ADCCTL1.bit.ADCPWDNZ = 1;
DelayUs(1000);
asm(" EDIS");
}
//###########################################################################
//
// FILE: F2837xD_GlobalVariableDefs.c
//
// TITLE: F2837xD Global Variables and Data Section Pragmas.
//
//###########################################################################
// $TI Release: F2837xD Support Library v3.02.00.00 $
// $Release Date: Sat Sep 16 15:29:00 CDT 2017 $
// $Copyright:
// Copyright (C) 2013-2017 Texas Instruments Incorporated - http://www.ti.com/
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions
// are met:
//
// Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
//
// Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in the
// documentation and/or other materials provided with the
// distribution.
//
// Neither the name of Texas Instruments Incorporated nor the names of
// its contributors may be used to endorse or promote products derived
// from this software without specific prior written permission.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
// $
//###########################################################################
#include "F2837xD_device.h" // F2837xD Headerfile Include File
//---------------------------------------------------------------------------
// Define Global Peripheral Variables:
//
//----------------------------------------
#ifdef __cplusplus
#pragma DATA_SECTION("AdcaRegsFile")
#else
#pragma DATA_SECTION(AdcaRegs,"AdcaRegsFile");
#endif
volatile struct ADC_REGS AdcaRegs;
#ifdef __cplusplus
#pragma DATA_SECTION("AdcbRegsFile")
#else
#pragma DATA_SECTION(AdcbRegs,"AdcbRegsFile");
#endif
volatile struct ADC_REGS AdcbRegs;
#ifdef __cplusplus
#pragma DATA_SECTION("AdccRegsFile")
#else
#pragma DATA_SECTION(AdccRegs,"AdccRegsFile");
#endif
volatile struct ADC_REGS AdccRegs;
#ifdef __cplusplus
#pragma DATA_SECTION("AdcdRegsFile")
#else
#pragma DATA_SECTION(AdcdRegs,"AdcdRegsFile");
#endif
volatile struct ADC_REGS AdcdRegs;
//----------------------------------------
#ifdef __cplusplus
#pragma DATA_SECTION("AdcaResultFile")
#else
#pragma DATA_SECTION(AdcaResultRegs,"AdcaResultFile");
#endif
volatile struct ADC_RESULT_REGS AdcaResultRegs;
//----------------------------------------
#ifdef __cplusplus
#pragma DATA_SECTION("AdcbResultFile")
#else
#pragma DATA_SECTION(AdcbResultRegs,"AdcbResultFile");
#endif
volatile struct ADC_RESULT_REGS AdcbResultRegs;
//----------------------------------------
#ifdef __cplusplus
#pragma DATA_SECTION("AdccResultFile")
#else
#pragma DATA_SECTION(AdccResultRegs,"AdccResultFile");
#endif
volatile struct ADC_RESULT_REGS AdccResultRegs;
//----------------------------------------
#ifdef __cplusplus
#pragma DATA_SECTION("AdcdResultFile")
#else
#pragma DATA_SECTION(AdcdResultRegs,"AdcdResultFile");
#endif
volatile struct ADC_RESULT_REGS AdcdResultRegs;
//----------------------------------------
#ifdef CPU1
#ifdef __cplusplus
#pragma DATA_SECTION("AnalogSubsysRegsFile")
#else
#pragma DATA_SECTION(AnalogSubsysRegs,"AnalogSubsysRegsFile");
#endif
volatile struct ANALOG_SUBSYS_REGS AnalogSubsysRegs;
#endif
#if __TI_COMPILER_VERSION__ >= 16006000
//----------------------------------------
#ifdef __cplusplus
#pragma DATA_SECTION("CanaRegsFile")
#else
#pragma DATA_SECTION(CanaRegs,"CanaRegsFile");
#endif
volatile struct CAN_REGS CanaRegs;
//----------------------------------------
#ifdef __cplusplus
#pragma DATA_SECTION("CanbRegsFile")
#else
#pragma DATA_SECTION(CanbRegs,"CanbRegsFile");
#endif
volatile struct CAN_REGS CanbRegs;
#endif
//----------------------------------------
#ifdef __cplusplus
#pragma DATA_SECTION("Cmpss1RegsFile")
#else
#pragma DATA_SECTION(Cmpss1Regs,"Cmpss1RegsFile");
#endif
volatile struct CMPSS_REGS Cmpss1Regs;
//----------------------------------------
#ifdef __cplusplus
#pragma DATA_SECTION("Cmpss2RegsFile")
#else
#pragma DATA_SECTION(Cmpss2Regs,"Cmpss2RegsFile");
#endif
volatile struct CMPSS_REGS Cmpss2Regs;
//----------------------------------------
#ifdef __cplusplus
#pragma DATA_SECTION("Cmpss3RegsFile")
#else
#pragma DATA_SECTION(Cmpss3Regs,"Cmpss3RegsFile");
#endif
volatile struct CMPSS_REGS Cmpss3Regs;
//----------------------------------------
#ifdef __cplusplus
#pragma DATA_SECTION("Cmpss4RegsFile")
#else
#pragma DATA_SECTION(Cmpss4Regs,"Cmpss4RegsFile");
#endif
volatile struct CMPSS_REGS Cmpss4Regs;
//----------------------------------------
#ifdef __cplusplus
#pragma DATA_SECTION("Cmpss5RegsFile")
#else
#pragma DATA_SECTION(Cmpss5Regs,"Cmpss5RegsFile");
#endif
volatile struct CMPSS_REGS Cmpss5Regs;
//----------------------------------------
#ifdef __cplusplus
#pragma DATA_SECTION("Cmpss6RegsFile")
#else
#pragma DATA_SECTION(Cmpss6Regs,"Cmpss6RegsFile");
#endif
volatile struct CMPSS_REGS Cmpss6Regs;
//----------------------------------------
#ifdef __cplusplus
#pragma DATA_SECTION("Cmpss7RegsFile")
#else
#pragma DATA_SECTION(Cmpss7Regs,"Cmpss7RegsFile");
#endif
volatile struct CMPSS_REGS Cmpss7Regs;
//----------------------------------------
#ifdef __cplusplus
#pragma DATA_SECTION("Cmpss8RegsFile")
#else
#pragma DATA_SECTION(Cmpss8Regs,"Cmpss8RegsFile");
#endif
volatile struct CMPSS_REGS Cmpss8Regs;
//----------------------------------------
#ifdef __cplusplus
#pragma DATA_SECTION("DacaRegsFile")
#else
#pragma DATA_SECTION(DacaRegs,"DacaRegsFile");
#endif
volatile struct DAC_REGS DacaRegs;
//----------------------------------------
#ifdef __cplusplus
#pragma DATA_SECTION("DacbRegsFile")
#else
#pragma DATA_SECTION(DacbRegs,"DacbRegsFile");
#endif
volatile struct DAC_REGS DacbRegs;
//----------------------------------------
#ifdef __cplusplus
#pragma DATA_SECTION("DaccRegsFile")
#else
#pragma DATA_SECTION(DaccRegs,"DaccRegsFile");
#endif
volatile struct DAC_REGS DaccRegs;
//----------------------------------------
#ifdef __cplusplus
#pragma DATA_SECTION("Cla1RegsFile")
#else
#pragma DATA_SECTION(Cla1Regs,"Cla1RegsFile");
#endif
volatile struct CLA_REGS Cla1Regs;
//----------------------------------------
#ifdef __cplusplus
#pragma DATA_SECTION("Cla1SoftIntRegsFile")
#else
#pragma DATA_SECTION(Cla1SoftIntRegs,"Cla1SoftIntRegsFile");
#endif
volatile struct CLA_SOFTINT_REGS Cla1SoftIntRegs;
//----------------------------------------
#ifdef __cplusplus
#pragma DATA_SECTION("ClkCfgRegsFile")
#else
#pragma DATA_SECTION(ClkCfgRegs,"ClkCfgRegsFile");
#endif
volatile struct CLK_CFG_REGS ClkCfgRegs;
//----------------------------------------
#ifdef __cplusplus
#pragma DATA_SECTION("CpuSysRegsFile")
#else
#pragma DATA_SECTION(CpuSysRegs,"CpuSysRegsFile");
#endif
volatile struct CPU_SYS_REGS CpuSysRegs;
//----------------------------------------
#ifdef __cplusplus
#pragma DATA_SECTION("CpuTimer0RegsFile")
#else
#pragma DATA_SECTION(CpuTimer0Regs,"CpuTimer0RegsFile");
#endif
volatile struct CPUTIMER_REGS CpuTimer0Regs;
//----------------------------------------
#ifdef __cplusplus
#pragma DATA_SECTION("CpuTimer1RegsFile")
#else
#pragma DATA_SECTION(CpuTimer1Regs,"CpuTimer1RegsFile");
#endif
volatile struct CPUTIMER_REGS CpuTimer1Regs;
//----------------------------------------
#ifdef __cplusplus
#pragma DATA_SECTION("CpuTimer2RegsFile")
#else
#pragma DATA_SECTION(CpuTimer2Regs,"CpuTimer2RegsFile");
#endif
volatile struct CPUTIMER_REGS CpuTimer2Regs;
//----------------------------------------
#ifdef __cplusplus
#pragma DATA_SECTION("DcsmZ1RegsFile")
#else
#pragma DATA_SECTION(DcsmZ1Regs,"DcsmZ1RegsFile");
#endif
volatile struct DCSM_Z1_REGS DcsmZ1Regs;
//----------------------------------------
#ifdef __cplusplus
#pragma DATA_SECTION("DcsmZ2RegsFile")
#else
#pragma DATA_SECTION(DcsmZ2Regs,"DcsmZ2RegsFile");
#endif
volatile struct DCSM_Z2_REGS DcsmZ2Regs;
//----------------------------------------
#ifdef __cplusplus
#pragma DATA_SECTION("DcsmCommonRegsFile")
#else
#pragma DATA_SECTION(DcsmCommonRegs,"DcsmCommonRegsFile");
#endif
volatile struct DCSM_COMMON_REGS DcsmCommonRegs;
//----------------------------------------
#ifdef __cplusplus
#pragma DATA_SECTION("DcsmZ1OtpFile")
#else
#pragma DATA_SECTION(DcsmZ1Otp,"DcsmZ1OtpFile");
#endif
volatile struct DCSM_Z1_OTP DcsmZ1Otp;
//----------------------------------------
#ifdef __cplusplus
#pragma DATA_SECTION("DcsmZ2OtpFile")
#else
#pragma DATA_SECTION(DcsmZ2Otp,"DcsmZ2OtpFile");
#endif
volatile struct DCSM_Z2_OTP DcsmZ2Otp;
//----------------------------------------
#ifdef __cplusplus
#pragma DATA_SECTION("DmaRegsFile")
#else
#pragma DATA_SECTION(DmaRegs,"DmaRegsFile");
#endif
volatile struct DMA_REGS DmaRegs;
//----------------------------------------
#ifdef __cplusplus
#pragma DATA_SECTION("DmaClaSrcSelRegsFile")
#else
#pragma DATA_SECTION(DmaClaSrcSelRegs,"DmaClaSrcSelRegsFile");
#endif
volatile struct DMA_CLA_SRC_SEL_REGS DmaClaSrcSelRegs;
//----------------------------------------
#ifdef CPU1
#ifdef __cplusplus
#pragma DATA_SECTION("DevCfgRegsFile")
#else
#pragma DATA_SECTION(DevCfgRegs,"DevCfgRegsFile");
#endif
volatile struct DEV_CFG_REGS DevCfgRegs;
#endif
//----------------------------------------
#ifdef __cplusplus
#pragma DATA_SECTION("ECap1RegsFile")
#else
#pragma DATA_SECTION(ECap1Regs,"ECap1RegsFile");
#endif
volatile struct ECAP_REGS ECap1Regs;
//----------------------------------------
#ifdef __cplusplus
#pragma DATA_SECTION("ECap2RegsFile")
#else
#pragma DATA_SECTION(ECap2Regs,"ECap2RegsFile");
#endif
volatile struct ECAP_REGS ECap2Regs;
//----------------------------------------
#ifdef __cplusplus
#pragma DATA_SECTION("ECap3RegsFile")
#else
#pragma DATA_SECTION(ECap3Regs,"ECap3RegsFile");
#endif
volatile struct ECAP_REGS ECap3Regs;
//----------------------------------------
#ifdef __cplusplus
#pragma DATA_SECTION("ECap4RegsFile")
#else
#pragma DATA_SECTION(ECap4Regs,"ECap4RegsFile");
#endif
volatile struct ECAP_REGS ECap4Regs;
//----------------------------------------
#ifdef __cplusplus
#pragma DATA_SECTION("ECap5RegsFile")
#else
#pragma DATA_SECTION(ECap5Regs,"ECap5RegsFile");
#endif
volatile struct ECAP_REGS ECap5Regs;
//----------------------------------------
#ifdef __cplusplus
#pragma DATA_SECTION("ECap6RegsFile")
#else
#pragma DATA_SECTION(ECap6Regs,"ECap6RegsFile");
#endif
volatile struct ECAP_REGS ECap6Regs;
//----------------------------------------
#ifdef __cplusplus
#pragma DATA_SECTION("Emif1RegsFile")
#else
#pragma DATA_SECTION(Emif1Regs,"Emif1RegsFile");
#endif
volatile struct EMIF_REGS Emif1Regs;
//----------------------------------------
#ifdef __cplusplus
#pragma DATA_SECTION("Emif2RegsFile")
#else
#pragma DATA_SECTION(Emif2Regs,"Emif2RegsFile");
#endif
volatile struct EMIF_REGS Emif2Regs;
//----------------------------------------
#ifdef __cplusplus
#pragma DATA_SECTION("EQep1RegsFile")
#else
#pragma DATA_SECTION(EQep1Regs,"EQep1RegsFile");
#endif
volatile struct EQEP_REGS EQep1Regs;
//----------------------------------------
#ifdef __cplusplus
#pragma DATA_SECTION("EQep2RegsFile")
#else
#pragma DATA_SECTION(EQep2Regs,"EQep2RegsFile");
#endif
volatile struct EQEP_REGS EQep2Regs;
//----------------------------------------
#ifdef __cplusplus
#pragma DATA_SECTION("EQep3RegsFile")
#else
#pragma DATA_SECTION(EQep3Regs,"EQep3RegsFile");
#endif
volatile struct EQEP_REGS EQep3Regs;
//----------------------------------------
#ifdef __cplusplus
#pragma DATA_SECTION("EPwm1RegsFile")
#else
#pragma DATA_SECTION(EPwm1Regs,"EPwm1RegsFile");
#endif
volatile struct EPWM_REGS EPwm1Regs;
//----------------------------------------
#ifdef __cplusplus
#pragma DATA_SECTION("EPwm2RegsFile")
#else
#pragma DATA_SECTION(EPwm2Regs,"EPwm2RegsFile");
#endif
volatile struct EPWM_REGS EPwm2Regs;
//----------------------------------------
#ifdef __cplusplus
#pragma DATA_SECTION("EPwm3RegsFile")
#else
#pragma DATA_SECTION(EPwm3Regs,"EPwm3RegsFile");
#endif
volatile struct EPWM_REGS EPwm3Regs;
//----------------------------------------
#ifdef __cplusplus
#pragma DATA_SECTION("EPwm4RegsFile")
#else
#pragma DATA_SECTION(EPwm4Regs,"EPwm4RegsFile");
#endif
volatile struct EPWM_REGS EPwm4Regs;
//----------------------------------------
#ifdef __cplusplus
#pragma DATA_SECTION("EPwm5RegsFile")
#else
#pragma DATA_SECTION(EPwm5Regs,"EPwm5RegsFile");
#endif
volatile struct EPWM_REGS EPwm5Regs;
//----------------------------------------
#ifdef __cplusplus
#pragma DATA_SECTION("EPwm6RegsFile")
#else
#pragma DATA_SECTION(EPwm6Regs,"EPwm6RegsFile");
#endif
volatile struct EPWM_REGS EPwm6Regs;
//----------------------------------------
#ifdef __cplusplus
#pragma DATA_SECTION("EPwm7RegsFile")
#else
#pragma DATA_SECTION(EPwm7Regs,"EPwm7RegsFile");
#endif
volatile struct EPWM_REGS EPwm7Regs;
//----------------------------------------
#ifdef __cplusplus
#pragma DATA_SECTION("EPwm8RegsFile")
#else
#pragma DATA_SECTION(EPwm8Regs,"EPwm8RegsFile");
#endif
volatile struct EPWM_REGS EPwm8Regs;
//----------------------------------------
#ifdef __cplusplus
#pragma DATA_SECTION("EPwm9RegsFile")
#else
#pragma DATA_SECTION(EPwm9Regs,"EPwm9RegsFile");
#endif
volatile struct EPWM_REGS EPwm9Regs;
//----------------------------------------
#ifdef __cplusplus
#pragma DATA_SECTION("EPwm10RegsFile")
#else
#pragma DATA_SECTION(EPwm10Regs,"EPwm10RegsFile");
#endif
volatile struct EPWM_REGS EPwm10Regs;
//----------------------------------------
#ifdef __cplusplus
#pragma DATA_SECTION("EPwm11RegsFile")
#else
#pragma DATA_SECTION(EPwm11Regs,"EPwm11RegsFile");
#endif
volatile struct EPWM_REGS EPwm11Regs;
//----------------------------------------
#ifdef __cplusplus
#pragma DATA_SECTION("EPwm12RegsFile")
#else
#pragma DATA_SECTION(EPwm12Regs,"EPwm12RegsFile");
#endif
volatile struct EPWM_REGS EPwm12Regs;
//----------------------------------------
#ifdef CPU1
#ifdef __cplusplus
#pragma DATA_SECTION("EPwmXbarRegsFile")
#else
#pragma DATA_SECTION(EPwmXbarRegs,"EPwmXbarRegsFile");
#endif
volatile struct EPWM_XBAR_REGS EPwmXbarRegs;
#endif
//----------------------------------------
#ifdef CPU1
#ifdef __cplusplus
#pragma DATA_SECTION("GpioCtrlRegsFile")
#else
#pragma DATA_SECTION(GpioCtrlRegs,"GpioCtrlRegsFile");
#endif
volatile struct GPIO_CTRL_REGS GpioCtrlRegs;
#endif
//----------------------------------------
#ifdef __cplusplus
#pragma DATA_SECTION("GpioDataRegsFile")
#else
#pragma DATA_SECTION(GpioDataRegs,"GpioDataRegsFile");
#endif
volatile struct GPIO_DATA_REGS GpioDataRegs;
//----------------------------------------
#ifdef CPU1
#ifdef __cplusplus
#pragma DATA_SECTION("InputXbarRegsFile")
#else
#pragma DATA_SECTION(InputXbarRegs,"InputXbarRegsFile");
#endif
volatile struct INPUT_XBAR_REGS InputXbarRegs;
#endif
//----------------------------------------
#ifdef CPU1
#ifdef __cplusplus
#pragma DATA_SECTION("XbarRegsFile")
#else
#pragma DATA_SECTION(XbarRegs,"XbarRegsFile");
#endif
volatile struct XBAR_REGS XbarRegs;
#endif
//----------------------------------------
#ifdef CPU1
#ifdef __cplusplus
#pragma DATA_SECTION("OutputXbarRegsFile")
#else
#pragma DATA_SECTION(OutputXbarRegs,"OutputXbarRegsFile");
#endif
volatile struct OUTPUT_XBAR_REGS OutputXbarRegs;
#endif
//----------------------------------------
#ifdef __cplusplus
#pragma DATA_SECTION("I2caRegsFile")
#else
#pragma DATA_SECTION(I2caRegs,"I2caRegsFile");
#endif
volatile struct I2C_REGS I2caRegs;
//----------------------------------------
#ifdef __cplusplus
#pragma DATA_SECTION("I2cbRegsFile")
#else
#pragma DATA_SECTION(I2cbRegs,"I2cbRegsFile");
#endif
volatile struct I2C_REGS I2cbRegs;
//----------------------------------------
#ifdef CPU1
#ifdef __cplusplus
#pragma DATA_SECTION("IpcRegsFile")
#else
#pragma DATA_SECTION(IpcRegs,"IpcRegsFile");
#endif
volatile struct IPC_REGS_CPU1 IpcRegs;
#endif
//----------------------------------------
#ifdef CPU2
#ifdef __cplusplus
#pragma DATA_SECTION("IpcRegsFile")
#else
#pragma DATA_SECTION(IpcRegs,"IpcRegsFile");
#endif
volatile struct IPC_REGS_CPU2 IpcRegs;
#endif
//----------------------------------------
#ifdef CPU1
#ifdef __cplusplus
#pragma DATA_SECTION("FlashPumpSemaphoreRegsFile")
#else
#pragma DATA_SECTION(FlashPumpSemaphoreRegs,"FlashPumpSemaphoreRegsFile");
#endif
volatile struct FLASH_PUMP_SEMAPHORE_REGS FlashPumpSemaphoreRegs;
#endif
//----------------------------------------
#ifdef CPU2
#ifdef __cplusplus
#pragma DATA_SECTION("FlashPumpSemaphoreRegsFile")
#else
#pragma DATA_SECTION(FlashPumpSemaphoreRegs,"FlashPumpSemaphoreRegsFile");
#endif
volatile struct FLASH_PUMP_SEMAPHORE_REGS FlashPumpSemaphoreRegs;
#endif
//----------------------------------------
#ifdef __cplusplus
#pragma DATA_SECTION("McbspaRegsFile")
#else
#pragma DATA_SECTION(McbspaRegs,"McbspaRegsFile");
#endif
volatile struct McBSP_REGS McbspaRegs;
//----------------------------------------
#ifdef CPU1
#ifdef __cplusplus
#pragma DATA_SECTION("RomPrefetchRegsFile")
#else
#pragma DATA_SECTION(RomPrefetchRegs,"RomPrefetchRegsFile");
#endif
volatile struct ROM_PREFETCH_REGS RomPrefetchRegs;
#endif
//----------------------------------------
#ifdef __cplusplus
#pragma DATA_SECTION("MemCfgRegsFile")
#else
#pragma DATA_SECTION(MemCfgRegs,"MemCfgRegsFile");
#endif
volatile struct MEM_CFG_REGS MemCfgRegs;
//----------------------------------------
#ifdef __cplusplus
#pragma DATA_SECTION("Emif1ConfigRegsFile")
#else
#pragma DATA_SECTION(Emif1ConfigRegs,"Emif1ConfigRegsFile");
#endif
volatile struct EMIF1_CONFIG_REGS Emif1ConfigRegs;
//----------------------------------------
#ifdef CPU1
#ifdef __cplusplus
#pragma DATA_SECTION("Emif2ConfigRegsFile")
#else
#pragma DATA_SECTION(Emif2ConfigRegs,"Emif2ConfigRegsFile");
#endif
volatile struct EMIF2_CONFIG_REGS Emif2ConfigRegs;
#endif
//----------------------------------------
#ifdef CPU1
#ifdef __cplusplus
#pragma DATA_SECTION("RomWaitStateRegsFile")
#else
#pragma DATA_SECTION(RomWaitStateRegs,"RomWaitStateRegsFile");
#endif
volatile struct ROM_WAIT_STATE_REGS RomWaitStateRegs;
#endif
//----------------------------------------
#ifdef __cplusplus
#pragma DATA_SECTION("AccessProtectionRegsFile")
#else
#pragma DATA_SECTION(AccessProtectionRegs,"AccessProtectionRegsFile");
#endif
volatile struct ACCESS_PROTECTION_REGS AccessProtectionRegs;
//----------------------------------------
#ifdef __cplusplus
#pragma DATA_SECTION("MemoryErrorRegsFile")
#else
#pragma DATA_SECTION(MemoryErrorRegs,"MemoryErrorRegsFile");
#endif
volatile struct MEMORY_ERROR_REGS MemoryErrorRegs;
//----------------------------------------
#ifdef __cplusplus
#pragma DATA_SECTION("McbspbRegsFile")
#else
#pragma DATA_SECTION(McbspbRegs,"McbspbRegsFile");
#endif
volatile struct McBSP_REGS McbspbRegs;
//----------------------------------------
#ifdef __cplusplus
#pragma DATA_SECTION("NmiIntruptRegsFile")
#else
#pragma DATA_SECTION(NmiIntruptRegs,"NmiIntruptRegsFile");
#endif
volatile struct NMI_INTRUPT_REGS NmiIntruptRegs;
//----------------------------------------
#ifdef __cplusplus
#pragma DATA_SECTION("PieCtrlRegsFile")
#else
#pragma DATA_SECTION(PieCtrlRegs,"PieCtrlRegsFile");
#endif
volatile struct PIE_CTRL_REGS PieCtrlRegs;
//----------------------------------------
#ifdef __cplusplus
#pragma DATA_SECTION("PieVectTableFile")
#else
#pragma DATA_SECTION(PieVectTable,"PieVectTableFile");
#endif
volatile struct PIE_VECT_TABLE PieVectTable;
//----------------------------------------
#ifdef __cplusplus
#pragma DATA_SECTION("SciaRegsFile")
#else
#pragma DATA_SECTION(SciaRegs,"SciaRegsFile");
#endif
volatile struct SCI_REGS SciaRegs;
//----------------------------------------
#ifdef __cplusplus
#pragma DATA_SECTION("ScibRegsFile")
#else
#pragma DATA_SECTION(ScibRegs,"ScibRegsFile");
#endif
volatile struct SCI_REGS ScibRegs;
//----------------------------------------
#ifdef __cplusplus
#pragma DATA_SECTION("ScicRegsFile")
#else
#pragma DATA_SECTION(ScicRegs,"ScicRegsFile");
#endif
volatile struct SCI_REGS ScicRegs;
//----------------------------------------
#ifdef __cplusplus
#pragma DATA_SECTION("ScidRegsFile")
#else
#pragma DATA_SECTION(ScidRegs,"ScidRegsFile");
#endif
volatile struct SCI_REGS ScidRegs;
//----------------------------------------
#ifdef __cplusplus
#pragma DATA_SECTION("SpiaRegsFile")
#else
#pragma DATA_SECTION(SpiaRegs,"SpiaRegsFile");
#endif
volatile struct SPI_REGS SpiaRegs;
//----------------------------------------
#ifdef __cplusplus
#pragma DATA_SECTION("SpibRegsFile")
#else
#pragma DATA_SECTION(SpibRegs,"SpibRegsFile");
#endif
volatile struct SPI_REGS SpibRegs;
//----------------------------------------
#ifdef __cplusplus
#pragma DATA_SECTION("SpicRegsFile")
#else
#pragma DATA_SECTION(SpicRegs,"SpicRegsFile");
#endif
volatile struct SPI_REGS SpicRegs;
//----------------------------------------
#ifdef __cplusplus
#pragma DATA_SECTION("Sdfm1RegsFile")
#else
#pragma DATA_SECTION(Sdfm1Regs,"Sdfm1RegsFile");
#endif
volatile struct SDFM_REGS Sdfm1Regs;
//----------------------------------------
#ifdef __cplusplus
#pragma DATA_SECTION("Sdfm2RegsFile")
#else
#pragma DATA_SECTION(Sdfm2Regs,"Sdfm2RegsFile");
#endif
volatile struct SDFM_REGS Sdfm2Regs;
//----------------------------------------
#ifdef CPU1
#ifdef __cplusplus
#pragma DATA_SECTION("SyncSocRegsFile")
#else
#pragma DATA_SECTION(SyncSocRegs,"SyncSocRegsFile");
#endif
volatile struct SYNC_SOC_REGS SyncSocRegs;
#endif
//----------------------------------------
#if defined(CPU1)
#ifdef __cplusplus
#pragma DATA_SECTION("UppRegsFile")
#else
#pragma DATA_SECTION(UppRegs,"UppRegsFile");
#endif
volatile struct UPP_REGS UppRegs;
#endif //defined(CPU1)
//----------------------------------------
#ifdef __cplusplus
#pragma DATA_SECTION("WdRegsFile")
#else
#pragma DATA_SECTION(WdRegs,"WdRegsFile");
#endif
volatile struct WD_REGS WdRegs;
//----------------------------------------
#ifdef __cplusplus
#pragma DATA_SECTION("XintRegsFile")
#else
#pragma DATA_SECTION(XintRegs,"XintRegsFile");
#endif
volatile struct XINT_REGS XintRegs;
//--------------------------------------
#ifdef __cplusplus
#pragma DATA_SECTION("EmuBModeVar");
#else
#pragma DATA_SECTION(EmuBMode,"EmuBModeVar");
#endif
Uint16 EmuBMode;
//----------------------------------------
#ifdef CPU1
#ifdef __cplusplus
#pragma DATA_SECTION("EmuBootPinsVar");
#else
#pragma DATA_SECTION(EmuBootPins,"EmuBootPinsVar");
#endif
Uint16 EmuBootPins;
#endif
//----------------------------------------
#ifdef __cplusplus
#pragma DATA_SECTION("Flash0EccRegsFile")
#else
#pragma DATA_SECTION(Flash0EccRegs,"Flash0EccRegsFile");
#endif
volatile struct FLASH_ECC_REGS Flash0EccRegs;
//----------------------------------------
#ifdef __cplusplus
#pragma DATA_SECTION("Flash0CtrlRegsFile")
#else
#pragma DATA_SECTION(Flash0CtrlRegs,"Flash0CtrlRegsFile");
#endif
volatile struct FLASH_CTRL_REGS Flash0CtrlRegs;
//===========================================================================
// End of file.
//===========================================================================
/**********************************************************************
* File: Main_6.c -- Solution File for Lab 6
* Devices: TMS320F28x7x
* Author: C2000 Technical Training, Texas Instruments
**********************************************************************/
#include "Lab.h" // Main include file
//--- Global Variables
Uint16 DEBUG_TOGGLE = 1; // Used for realtime mode investigation test
Uint16 SINE_ENABLE = 0; // Used for DAC waveform generation
Uint16 Adca1Buf[ADC_BUF_LENa1]; // ADC buffer allocation************mz
Uint16 Adca2Buf[ADC_BUF_LENa2]; // ADC buffer1 allocation************mz
Uint16 Adca3Buf[ADC_BUF_LENa3]; // ADC buffer1 allocation************mz
Uint16 Adcb1Buf[ADC_BUF_LENb1]; // ADC buffer allocation************mz
Uint16 Adcb2Buf[ADC_BUF_LENb2]; // ADC buffer1 allocation************mz
Uint16 Adcb3Buf[ADC_BUF_LENb3]; // ADC buffer1 allocation************mz
Uint16 Adcc1Buf[ADC_BUF_LENc1]; // ADC buffer allocation************mz
Uint16 Adcc2Buf[ADC_BUF_LENc2]; // ADC buffer1 allocation************mz
Uint16 Adcc3Buf[ADC_BUF_LENc3]; // ADC buffer1 allocation************mz
Uint16 DacOffset; // DAC offset
Uint16 DacOutput; // DAC output
/*uint16_t adcAResult0;
uint16_t adcAResult1;
uint16_t adcAResult2;
uint16_t adcBResult0;
uint16_t adcBResult1;
uint16_t adcBResult2;
uint16_t adcCResult0;
uint16_t adcCResult1;
uint16_t adcCResult2;
*/
// Function Prototypes
//
void configureADC(uint32_t adcBase);
void initEPWM();
void initADCSOC(void);
__interrupt void adcA1ISR(void);
//****************************************************************2-19-2020
//
/**********************************************************************
* Function: main()
*
* Description: Main function for C28x workshop labs
**********************************************************************/
void main(void)
{
//--- CPU Initialization
InitSysCtrl(); // Initialize the CPU (FILE: SysCtrl.c)
InitGpio(); // Initialize the shared GPIO pins (FILE: Gpio.c)
InitXbar(); // Initialize the input, output & ePWM X-Bar (FILE: Xbar.c)
InitPieCtrl(); // Initialize and enable the PIE (FILE: PieCtrl.c)
InitWatchdog(); // Initialize the Watchdog Timer (FILE: WatchDog.c)
//--- Peripheral Initialization
InitAdca(); // Initialize the ADC-A (FILE: Adc.c)
InitDacb(); // Initialize the DAC-B (File: Dac.c)
InitEPwm(); // Initialize the EPwm (FILE: EPwm.c)
InitAdcb(); // Initialize the ADC-A (FILE: Adc.c)********MZ
InitAdcc(); // Initialize the ADC-A (FILE: Adc.c)********MZ
//--- Enable global interrupts
asm(" CLRC INTM, DBGM"); // Enable global interrupts and realtime debug
//--- Main Loop
while(1) // endless loop - wait for an interrupt
{
asm(" NOP");
}
} //end of main()
/*** end of file *****************************************************/