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TMS320F28379D: Delay beetween two PWM (a slave and a master)

Guillaume katan
Intellectual 855 points

Part Number: TMS320F28379D

Hi everyone,

I am working on a phase shift converter design and I am trying to have one fixed PWM (4) and an other one (5) which can be dephased. The two PWMs have the same duty cycle (50% minus deadband). I have everything done but I have a little delay beetween the both PWM of 20ns (I noticed that it is one step of my counter).

I also noticed by debugging step by step that the EPWM4regs.bit.TBCTR and EPWM5regs.bit.TBCTR have a difference of 2...

I attached picture too understand everything.

Thank you in advance !

Debugging :

My code :

Pwm Signal D0 is PWM4 and D2 is PWM5:

  • 0
    TI__Expert 7210 points

    Hi Guillaume,

    Can you highlighting on how are you starting the PWMs? The PCLKCR2 for EPWM4 and EPWM5 register has to be enabled first while keeping the PCLKCR0.TBCLKSYNC bit in reset. Is that the process that you've followed?

    Also, can you state on how are you trying to synchronize PWMs in the example code?

    Thanks,

    Aditya

  • 0 in reply to Aditya Dholakia
    Intellectual 855 points

    Hi Aditya,

    I think I am doing everything well and I can't synchronize perfectly the PWM according to the datasheet of the F28379D on the 14.4.3.3 :

    "The value of the phase register is loaded into the counter register when an input synchronization pulse
    is detected (TBPHS → TBCTR). This operation occurs on the next valid time-base clock (TBCLK)
    edge.
    The delay from internal master module to slave modules is given by:
    – if ( TBCLK = EPWMCLK): 2 x EPWMCLK
    – if ( TBCLK != EPWMCLK):1 TBCLK"

    I changed my configuration to win the 2 CLK missing and I have my signals working !

    Thank you anyway for your help !

  • +1 in reply to Guillaume katan
    TI__Expert 7210 points

    Hi,

    Very glad to hear that you resolved this. Something that I missed as well. Thanks for the information.

    Can you also please mark your answer as 'Resolved' so that we can close this thread?

    Regards,

    Aditya