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TMS320F280049C: 280049 ADC sample question

Foriner
Intellectual 425 points
Part Number: TMS320F280049C

Now my project switch from 28032 to 280049.

When i use 280049 ADC to sample a volt, i find is lower than actual voltage. the schematic diagram is below:

i use both A4 and A5 to sample , both lower than actual voltage. but in 28032 project , is ok. 

i compare 28032 and 280049 , the Ron is very different, the 280049 project sample window is 8:

#define SAMPLE_WINDOW   0x8  // S/H width in ADC module periods

28032:

280049:

Is this the cause of the problem? tks

?

  • 0
    TI__Guru 60865 points

    Hi Foriner,

    Are you setting the S+H window to '8' on F28004x?  One difference between the device families is that F2803x S+H is based on ADCCLK (60MHz or 30MHz) while F28004x S+H is based on SYSCLK (100MHz).  (1/30MHz)*8 = 267ns whereas (1/100MHz)*8 = 80ns.  The settling speed is also a little slower on F28004x (R-C time constant of the input).

    Either way, the correct value for the S+H depends on both the internal input model and the impedance of your external circuit.  It is strongly recommended that you use simulation to determine the appropriate S+H window: https://www.ti.com/lit/an/spract6/spract6.pdf 

  • 0 in reply to Devin Cottier
    Intellectual 425 points

    thank you, i have attempted to change S+H window from "8" to "16", seem no effect. 

    no consider ADCCLK 100M or 60M, according to 280049 datasheet, the Ch and Cp is higher than 28032

    whis mean 280049 need more S+H window time?

  • 0 in reply to Foriner
    TI__Guru 60865 points

    Hi Foriner,

    The R-C time constant of Ch + Ron for F28004x is slightly higher than F2803x, so F28004x might require slightly more S+H time.

    However, the required S+H time is highly dependent on the external circuit driving the ADC, so determining the S+H time via simulation is strongly recommended. 

    Also note that the S+H is based on ADCCLK on F2803x (30MHz or 60MHz) whereas it is based on SYSCLK for F28004x (100MHz)

  • 0 in reply to Devin Cottier
    Intellectual 425 points

    i got your suggestion, but the volt input have a R=2K and C=4.7nF low past filter, so the ideal S+H time is very long

    how can i deal this question, now i find 280049's AD have a very bad performance in sample volt with above low past filter, the sample err reach up to  1.5%

  • 0 in reply to Foriner
    TI__Guru 60865 points

    Hi Foriner,

    That's a pretty aggressive low-pass filter for the drive stage of any ADC.  Usually input settling needs to be the major design consideration of the stage directly driving the ADC input, while getting some mild low-pass filtering is nice if other design considerations have some margin.  For a more aggressive LP filter, you'd usually need to add a dedicated filter stage before the ADC drive stage.    

    Depending on the sample rate that you need, you could use a charge-sharing input design (higher C, lower R) to get some low-pass filtering while also achieving good settling performance.  See https://www.ti.com/lit/an/spracv0/spracv0.pdf for the design flow.

    If that input design doesn't work, you can also try the error (memory cross-talk error specifically) mitigation strategies presented in this application report: https://www.ti.com/lit/an/spracw9/spracw9.pdf