Hello,
I want to know function of TRST pin in DSP TMS320F28335?
Xilinx/ Altera FPGAs can program only on 4 Pins of JTAG (TDO, TDI, TCK, TMS), then why DSP needs TRST pin?
Thanks in advance.
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Hello,
I want to know function of TRST pin in DSP TMS320F28335?
Xilinx/ Altera FPGAs can program only on 4 Pins of JTAG (TDO, TDI, TCK, TMS), then why DSP needs TRST pin?
Thanks in advance.
Anshuman,
The TRSTn pin is an optional(but defined) part of the JTAG/IEEE 1149.1 standard. It is an active low signal used to keep the test logic in a reset state.
It is used in most TI DSP/MCU devices to gate the test logic vs a scan sequence on TCK/TMS that devices without this pin employ.
At any rate, bringing this pin out of reset(low to high pin state: 0->3.3V) is necessary to debug the device through the debug probe/JTAG connection.
Specific to the F2833x device(and other C2000 MCUs) the rising edge of TRSTn also latches the state of the EMU0 and EMU1 pins. For normal debug connection you should have a pullup on both these pins(2.2kOhm-4.7kOhm) so that the latched state is high.
For normal device operation(debugger not connected) TRSTn needs to remain "low", we recommend placing a 2.2kOhm pull-down on this pin hold the test logic in reset.
Best,
Matthew