TMS320F28379D: How to align the hardware triggers from 2 CPUs of TMS320F28379D

Hi Kunihide,

Can you please describe what kind of trigger you are trying to align? Providing some code for this part would also be helpful in understanding how things are setup.

Best Regards,

Marlyn

Hello Merlin

Create an executable file for each of CPU1 and CPU2, and generate PWM pulses that are synchronized from ePWM1 to ePWM8 and operated at the same frequency.
However, the phases of ePWM1 to ePWM4 and ePWM5 to ePWM8 are fixed and out of phase.
ePWM1 and ePWM2 set a trigger for ADC capture and control writing from ePWM3 to the shadow memory of ePWM1 to ePWM4. Similarly, writing from ePWM7 to the shadow memory of ePWM5 to ePWM8 is controlled.
This is because it uses a setting that issues a hardware interrupt at half the PWM frequency.
The reason why writing to the shadow memory is controlled by the hardware interrupt is that if the result calculated in the hardware interrupt is set to the shadow memory as it is, the timing of reflection is changed depending on the calculation load.
The phase is matched by the PHS setting, but the trigger output shifts or shifts at the same time each time the microcomputer is started.

I set CPU1 and CPU2 to operate at the same time on the CCS settings and tried to execute them, but even with this, the interrupt pattern of the hardware interrupt changed every time the microcomputer was started.

Hi Kunihide,

Kunihide Hirai said:

I set CPU1 and CPU2 to operate at the same time on the CCS settings and tried to execute them, but even with this, the interrupt pattern of the hardware interrupt changed every time the microcomputer was started.

Are you using the GBCLKSYNC bit instead of the TBCLKSYNC bit to start all of your pwm waveforms at the same time? If not, I would highly encourage you to do this. GBCLKSYNC will start the time base counter for all of the enabled pwm modules for both CPU1 and CPU2.

Best Regards,

Marlyn

Hi Marlyn

I found a description of the function pointed out in 15.4.3.2 Time-Base Clock Synchronization of the Technical Reference Manual (Rev. I).
I will tell the person in charge and check it.

Hi Marlyn

When I checked the initialization code of CPU1 and CPU2, I found that the procedure of "15.4.3.2 Time-Base Clock Synchronization" was repeated for each module with the following structure.

// Excerpt of initialization code
EALLOW;
CpuSysRegs.PCLKCR2.bit.EPWM1 = 1;
CpuSysRegs.PCLKCR0.bit.TBCLKSYNC = 0;
EDIS;

// ePWM1 initialization code

EALLOW;
CpuSysRegs.PCLKCR0.bit.TBCLKSYNC = 1;
EDIS;

EALLOW;
CpuSysRegs.PCLKCR2.bit.EPWM2 = 1;
CpuSysRegs.PCLKCR0.bit.TBCLKSYNC = 0;
EDIS;

// ePWM2 initialization code

EALLOW;
CpuSysRegs.PCLKCR0.bit.TBCLKSYNC = 1;
EDIS;

EALLOW;
CpuSysRegs.PCLKCR2.bit.EPWM3 = 1;
CpuSysRegs.PCLKCR0.bit.TBCLKSYNC = 0;
EDIS;

// ePWM3 initialization code

EALLOW;
CpuSysRegs.PCLKCR0.bit.TBCLKSYNC = 1;
EDIS;

EALLOW;
CpuSysRegs.PCLKCR2.bit.EPWM4 = 1;
CpuSysRegs.PCLKCR0.bit.TBCLKSYNC = 0;
EDIS;

// ePWM4 initialization code

EALLOW;
CpuSysRegs.PCLKCR0.bit.TBCLKSYNC = 1;
EDIS;

Hi Marlyn

It is implemented as follows with reference to the code that was uploaded.
When I try to check if it can be built, it seems that the path of "waitForCpu2ReadySignal ()" does not pass and an error occurs.
In what file is waitForCpu2ReadySignal implemented?
The compiler version and code use the following.
soft Version: 8.3.1.00004

compiler version: TI v16.9.2.LTS
Code: controlSUITE \ device_support \ F2837xD \ v190
The code I'm trying to implement is:

Hi Marlyn

I made a tentative model because I don't know the location of the "waitForCpu2ReadySignal" and "sendReadySignalToCPU1" functions.
I have already assigned some CHANNEL for CPU-to-CPU communication, so I put in a code to send information to a free CHANNEL.
However, even if I added a code to set "GTBCLKSYNC = 1" after communication between CPUs, as a result of checking from CCS, Falg did not change.
The added code is as follows.

// CPU1 side receiver
loopCond = true;
while (loopCond) {
MW_IPC_Receive (CHANNEL3, (uint32_t *)& TestModel.IPCReceive_o1_Channel3, & TestModel.IPCReceive_o2_Channel3, 1, 5, 0);

loopCond =! TestModel.IPCReceive_o1_Channel3;
}

CpuSysRegs.PCLKCR0.bit.GTBCLKSYNC = 1;

// CPU2 side transmitter
Initial_Complete_Value = 1;
MW_IPC_Transmit (CHANNEL3, (uint32_t *) & Initial_Complete_Value, 1, 5, 0);