TMS320F28379D: How can I set up TTBCLK

Hi Mingi,

The epwm_ex8_deadband configures the epwm modules in up down count mode. For this mode the Tpwm is calculated by,

T_pwm = 2(TBPRD)(T_TBCLK)

In the example TBPRD is configured as 2000

T_TBCLK = 1/ (EPWMCLK / (HSPCLKDIV x CLKDIV))

The example configured HSPCLKDIV and CLKDIV using the following function: 

    //
    // Set ePWM clock pre-scaler
    //
    EPWM_setClockPrescaler(base,
                           EPWM_CLOCK_DIVIDER_4,
                           EPWM_HSCLOCK_DIVIDER_4);

So, in this case, HSPCLKDIV x CLKDIV = 4*4 = 16

To find EPWMCLK, we'll see that EPWMCLK comes from SYSCLK and then a divider (EPWMCLKDIV) which has a default of /2. This is so because while the max SYSCLK is 200MHz, the EPWMCLK max is 100 MHz.

With the above, EPWMCLK should be 100MHz.

T_TBCLK = 1/ (100MHz / 16) = 160 nsec 

T_pwm = 2(TBPRD)(T_TBCLK) = 2(2000)(160ns) = .00064

Fpwm = 1/Tpwm = 1/.00064 = ~ 1562 Hz

The reason you are seeing something else is that you might not be using the _LAUNCHXL_F28379D predefine symbol. Within the device.h file, the SYSCLK is setup by changing the PLL settings. The examples are setup by default to configure the clock settings with a 20MHz input clock, but the launchpad actually has a 10MHz input clock.

If you do not include the predefine then the SYSCLK will be setup as 100MHz and therefore EPWMCLK will be 50MHz.

Redoing the equations with 50MHz:

T_TBCLK = 1/ (50MHz / 16) = 320 nsec

T_pwm = 2(TBPRD)(T_TBCLK) = 2(2000)(320ns) = .00128

Fpwm = 1/Tpwm = 1/.00128 = ~ 781.25 Hz

//
// Launchpad Configuration
//
#ifdef _LAUNCHXL_F28379D

//
// 10MHz XTAL on LaunchPad. For use with SysCtl_getClock().
//
#define DEVICE_OSCSRC_FREQ          10000000U

//
// Define to pass to SysCtl_setClock(). Will configure the clock as follows:
// PLLSYSCLK = 10MHz (XTAL_OSC) * 40 (IMULT) * 1 (FMULT) / 2 (PLLCLK_BY_2)
//
#define DEVICE_SETCLOCK_CFG         (SYSCTL_OSCSRC_XTAL | SYSCTL_IMULT(40) |  \
                                     SYSCTL_FMULT_NONE | SYSCTL_SYSDIV(2) |   \
                                     SYSCTL_PLL_ENABLE)

//
// 200MHz SYSCLK frequency based on the above DEVICE_SETCLOCK_CFG. Update the
// code below if a different clock configuration is used!
//
#define DEVICE_SYSCLK_FREQ          ((DEVICE_OSCSRC_FREQ * 40 * 1) / 2)

//
// ControlCARD Configuration
//
#else

//
// 20MHz XTAL on controlCARD. For use with SysCtl_getClock().
//
#define DEVICE_OSCSRC_FREQ          20000000U

//
// Define to pass to SysCtl_setClock(). Will configure the clock as follows:
// PLLSYSCLK = 20MHz (XTAL_OSC) * 20 (IMULT) * 1 (FMULT) / 2 (PLLCLK_BY_2)
//
#define DEVICE_SETCLOCK_CFG         (SYSCTL_OSCSRC_XTAL | SYSCTL_IMULT(20) |  \
                                     SYSCTL_FMULT_NONE | SYSCTL_SYSDIV(2) |   \
                                     SYSCTL_PLL_ENABLE)

//
// 200MHz SYSCLK frequency based on the above DEVICE_SETCLOCK_CFG. Update the
// code below if a different clock configuration is used!
//
#define DEVICE_SYSCLK_FREQ          ((DEVICE_OSCSRC_FREQ * 20 * 1) / 2)

#endif

To include the predefine in your project:

- Right click on your project -> Click 'Properties'

- Go to 'Build' -> 'C2000 Compiler' -> 'Predefine Symbols' 

- Click the file with a plus sign icon and add the predefine _LAUNCHXL_F28379D

Best Regards,

Marlyn

Hi Mingi,

Mingi Oh said:

1) where can I change the EPWMCLKDIV?

Within the 'sysctl.h' file there is the following function:

//*****************************************************************************
//
//! Sets the ePWM clock divider.
//!
//! \param divider is the value by which PLLSYSCLK is divided
//!
//! This function configures the clock rate of the EPWMCLK. The
//! \e divider parameter is the value by which the SYSCLK rate is divided to
//! get the EPWMCLK rate. For example, \b SYSCTL_EPWMCLK_DIV_2 will select an
//! EPWMCLK rate that is half the PLLSYSCLK rate.
//!
//! \return None.
//
//*****************************************************************************
static inline void
SysCtl_setEPWMClockDivider(SysCtl_EPWMCLKDivider divider)
{
    //
    // Write the divider selection to the appropriate register.
    //
    EALLOW;
    HWREGH(CLKCFG_BASE + SYSCTL_O_PERCLKDIVSEL) =
        (HWREGH(CLKCFG_BASE + SYSCTL_O_PERCLKDIVSEL) &
         ~SYSCTL_PERCLKDIVSEL_EPWMCLKDIV_M) | (uint16_t)divider;
    EDIS;
}

With the following input parameter options:

//*****************************************************************************
//
//! The following are values that can be passed to SysCtl_setEPWMClockDivider()
//! as the \e divider parameter.
//
//*****************************************************************************
typedef enum
{
    SYSCTL_EPWMCLK_DIV_1,           //!< EPWMCLK = PLLSYSCLK / 1
    SYSCTL_EPWMCLK_DIV_2            //!< EPWMCLK = PLLSYSCLK / 2
} SysCtl_EPWMCLKDivider;

So to change the EPWMCLKDIV you can insert the following line of code into your .c file before you initialize the epwm modules:

 SysCtl_setEPWMClockDivider(SYSCTL_EPWMCLK_DIV_2);

Mingi Oh said:

2) Is there any proper method for setting the T_TBCLK?

This value is depended on EPWMCLK, HSPCLKDIV, and CLKDIV. That being said, as long as EPWMCLK is not greater than the datasheet max (100MHz) there is no one proper way to configure T_TBCLK. This is dependent on the values you are trying to achieve. 

Best Regards,

Marlyn