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TMS320F28388D: CCS register view for the CM UART are not correct

Jbec
Prodigy 175 points
Part Number: TMS320F28388D


Hi,  I'm having some issues with displaying the CM register view for this device. The UART0 registers are not correct.

CCS 10.4

The reference manual (SPRUII0C) on page 5162 indicates that the register addresses are aligned on 4 byte boundaries.  However, the registers in the CCS register view are on 2 byte boundaries. Following is a screen shot of the UART0 control register

According to the ref manual this register's offset from base should be 0x30.  If I Right click on UARTCTL and select 'View Memory At Address' I get this:

Note that the memory address highlighted is 0x4000C018.  So, the CCS Registers view is displaying the wrong address.  Why is this?

  • 0
    TI__Mastermind 36305 points

    Hi, 

    What is the CCS version that you are using?

    Best Regards

    Siddharth

  • 0 in reply to Siddharth Deshpande
    Prodigy 175 points

     CCS version 10.4.0.00006

  • 0 in reply to Jbec
    TI__Mastermind 36305 points

    Hi ,

    Looks like it is an issue with the xml file located at <CCSInstallDir>/ccs_base/common/targetdb/Modules/C2000/f2838x_cm_uart_regs.xml file.

    Will report this issue to the development team and try to provide a workaround. 

    Best Regards

    Siddharth

  • 0 in reply to Siddharth Deshpande
    Prodigy 175 points

    I edited the file you indicated, doubling each of the register offsets.  The UART register display looks correct now.  Are any of the other .xml files in that directory (for F2838x) wrong? 

  • 0 in reply to Jbec
    TI__Mastermind 36305 points

    Glad that your were able to resolve it. 

    Request you to post/attach the updated xml file in this thread so that if any other forum member , we can point them to this thread. 

    We will include the correct xml file in the next CCS release.

    Best Regards

    Siddharth

  • 0 in reply to Siddharth Deshpande
    Prodigy 175 points

    The requested file.  

    Fullscreen f2838x_cm_uart_regs.xml Download 
    <module id="UART_REGS" HW_revision="" description="UART Registers">
	<register id="UARTDR" width="32" page="1" offset="0x0" internal="0" description="UART Data">
		<bitfield id="DATA" description="Data Transmitted or Received" begin="7" end="0" width="8" rwaccess="RW"/>
		<bitfield id="FE" description="UART Framing Error" begin="8" end="8" width="1" rwaccess="R"/>
		<bitfield id="PE" description="UART Parity Error" begin="9" end="9" width="1" rwaccess="R"/>
		<bitfield id="BE" description="UART Break Error" begin="10" end="10" width="1" rwaccess="R"/>
		<bitfield id="OE" description="UART Overrun Error" begin="11" end="11" width="1" rwaccess="R"/>
	</register>
	<register id="UARTRSR" width="32" page="1" offset="0x4" internal="0" description="UART Receive Status/Error Clear">
		<bitfield id="FE" description="UART Framing Error" begin="0" end="0" width="1" rwaccess="R"/>
		<bitfield id="PE" description="UART Parity Error" begin="1" end="1" width="1" rwaccess="R"/>
		<bitfield id="BE" description="UART Break Error" begin="2" end="2" width="1" rwaccess="R"/>
		<bitfield id="OE" description="UART Overrun Error" begin="3" end="3" width="1" rwaccess="R"/>
	</register>
	<register id="UARTFR" width="32" page="1" offset="0x18" internal="0" description="UART Flag">
		<bitfield id="BUSY" description="UART Busy" begin="3" end="3" width="1" rwaccess="R"/>
		<bitfield id="RXFE" description="UART Receive FIFO Empty" begin="4" end="4" width="1" rwaccess="R"/>
		<bitfield id="TXFF" description="UART Transmit FIFO Full" begin="5" end="5" width="1" rwaccess="R"/>
		<bitfield id="RXFF" description="UART Receive FIFO Full" begin="6" end="6" width="1" rwaccess="R"/>
		<bitfield id="TXFE" description="UART Transmit FIFO Empty" begin="7" end="7" width="1" rwaccess="R"/>
	</register>
	<register id="UARTILPR" width="32" page="1" offset="0x20" internal="0" description="UART IrDA Low-Power Register">
		<bitfield id="ILPDVSR" description="IrDA Low-Power Divisor" begin="7" end="0" width="8" rwaccess="RW"/>
	</register>
	<register id="UARTIBRD" width="32" page="1" offset="0x24" internal="0" description="UART Integer Baud-Rate Divisor">
		<bitfield id="DIVINT" description="Integer Baud-Rate Divisor" begin="15" end="0" width="16" rwaccess="RW"/>
	</register>
	<register id="UARTFBRD" width="32" page="1" offset="0x28" internal="0" description="UART Fractional Baud-Rate Divisor">
		<bitfield id="DIVFRAC" description="Fractional Baud-Rate Divisor" begin="5" end="0" width="6" rwaccess="RW"/>
	</register>
	<register id="UARTLCRH" width="32" page="1" offset="0x2c" internal="0" description="UART Line Control">
		<bitfield id="BRK" description="UART Send Break" begin="0" end="0" width="1" rwaccess="RW"/>
		<bitfield id="PEN" description="UART Parity Enable" begin="1" end="1" width="1" rwaccess="RW"/>
		<bitfield id="EPS" description="UART Even Parity Select" begin="2" end="2" width="1" rwaccess="RW"/>
		<bitfield id="STP2" description="UART Two Stop Bits Select" begin="3" end="3" width="1" rwaccess="RW"/>
		<bitfield id="FEN" description="UART Enable FIFOs" begin="4" end="4" width="1" rwaccess="RW"/>
		<bitfield id="WLEN" description="UART Word Length" begin="6" end="5" width="2" rwaccess="RW"/>
		<bitfield id="SPS" description="UART Stick Parity Select" begin="7" end="7" width="1" rwaccess="RW"/>
	</register>
	<register id="UARTCTL" width="32" page="1" offset="0x30" internal="0" description="UART Control">
		<bitfield id="UARTEN" description="UART Enable" begin="0" end="0" width="1" rwaccess="RW"/>
		<bitfield id="SIREN" description="UART SIR Enable" begin="1" end="1" width="1" rwaccess="RW"/>
		<bitfield id="SIRLP" description="UART SIR Low-Power Mode" begin="2" end="2" width="1" rwaccess="RW"/>
		<bitfield id="EOT" description="End of Transmission" begin="4" end="4" width="1" rwaccess="RW"/>
		<bitfield id="HSE" description="High-Speed Enable" begin="5" end="5" width="1" rwaccess="RW"/>
		<bitfield id="LBE" description="UART Loop Back Enable" begin="7" end="7" width="1" rwaccess="RW"/>
		<bitfield id="TXE" description="UART Transmit Enable " begin="8" end="8" width="1" rwaccess="RW"/>
		<bitfield id="RXE" description="UART Receive Enable" begin="9" end="9" width="1" rwaccess="RW"/>
	</register>
	<register id="UARTIFLS" width="32" page="1" offset="0x34" internal="0" description="UART Interrupt FIFO Level Select">
		<bitfield id="TXIFLSEL" description="UART Transmit Interrupt FIFO Level Select" begin="2" end="0" width="3" rwaccess="RW"/>
		<bitfield id="RXIFLSEL" description="UART Receive Interrupt FIFO Level Select" begin="5" end="3" width="3" rwaccess="RW"/>
	</register>
	<register id="UARTIM" width="32" page="1" offset="0x38" internal="0" description="UART Interrupt Mask">
		<bitfield id="RXIM" description="UART Receive Interrupt Mask" begin="4" end="4" width="1" rwaccess="RW"/>
		<bitfield id="TXIM" description="UART Transmit Interrupt Mask" begin="5" end="5" width="1" rwaccess="RW"/>
		<bitfield id="RTIM" description="UART Receive Time-Out Interrupt Mask " begin="6" end="6" width="1" rwaccess="RW"/>
		<bitfield id="FEIM" description="UART Framing Error Interrupt Mask" begin="7" end="7" width="1" rwaccess="RW"/>
		<bitfield id="PEIM" description="UART Parity Error Interrupt Mask" begin="8" end="8" width="1" rwaccess="RW"/>
		<bitfield id="BEIM" description="UART Break Error Interrupt Mask" begin="9" end="9" width="1" rwaccess="RW"/>
		<bitfield id="OEIM" description="UART Overrun Error Interrupt Mask" begin="10" end="10" width="1" rwaccess="RW"/>
		<bitfield id="9BITIM" description="9-Bit Mode Interrupt Mask" begin="12" end="12" width="1" rwaccess="RW"/>
		<bitfield id="DMARXIM" description="Receive DMA Interrupt Mask" begin="16" end="16" width="1" rwaccess="RW"/>
		<bitfield id="DMATXIM" description="Transmit DMA Interrupt Mask" begin="17" end="17" width="1" rwaccess="RW"/>
	</register>
	<register id="UARTRIS" width="32" page="1" offset="0x3c" internal="0" description="UART Raw Interrupt Status">
		<bitfield id="RXRIS" description="UART Receive Raw Interrupt Status" begin="4" end="4" width="1" rwaccess="R"/>
		<bitfield id="TXRIS" description="UART Transmit Raw Interrupt Status" begin="5" end="5" width="1" rwaccess="R"/>
		<bitfield id="RTRIS" description="UART Receive Time-Out Raw Interrupt Status" begin="6" end="6" width="1" rwaccess="R"/>
		<bitfield id="FERIS" description="UART Framing Error Raw Interrupt Status" begin="7" end="7" width="1" rwaccess="R"/>
		<bitfield id="PERIS" description="UART Parity Error Raw Interrupt Status" begin="8" end="8" width="1" rwaccess="R"/>
		<bitfield id="BERIS" description="UART Break Error Raw Interrupt Status" begin="9" end="9" width="1" rwaccess="R"/>
		<bitfield id="OERIS" description="UART Overrun Error Raw Interrupt Status" begin="10" end="10" width="1" rwaccess="R"/>
		<bitfield id="9BITRIS" description="9-Bit Mode Raw Interrupt Status" begin="12" end="12" width="1" rwaccess="R"/>
		<bitfield id="DMARXRIS" description="Receive DMA Raw Interrupt Status" begin="16" end="16" width="1" rwaccess="R"/>
		<bitfield id="DMATXRIS" description="Transmit DMA Raw Interrupt Status" begin="17" end="17" width="1" rwaccess="R"/>
	</register>
	<register id="UARTMIS" width="32" page="1" offset="0x40" internal="0" description="UART Masked Interrupt Status">
		<bitfield id="RXMIS" description="UART Receive Masked Interrupt Status" begin="4" end="4" width="1" rwaccess="R"/>
		<bitfield id="TXMIS" description="UART Transmit Masked Interrupt Status" begin="5" end="5" width="1" rwaccess="R"/>
		<bitfield id="RTMIS" description="UART Receive Time-Out Masked Interrupt Status" begin="6" end="6" width="1" rwaccess="R"/>
		<bitfield id="FEMIS" description="UART Framing Error Masked Interrupt Status" begin="7" end="7" width="1" rwaccess="R"/>
		<bitfield id="PEMIS" description="UART Parity Error Masked Interrupt Status" begin="8" end="8" width="1" rwaccess="R"/>
		<bitfield id="BEMIS" description="UART Break Error Masked Interrupt Status" begin="9" end="9" width="1" rwaccess="R"/>
		<bitfield id="OEMIS" description="UART Overrun Error Masked Interrupt Status" begin="10" end="10" width="1" rwaccess="R"/>
		<bitfield id="9BITMIS" description="9-Bit Mode Masked Interrupt Status" begin="12" end="12" width="1" rwaccess="R"/>
		<bitfield id="DMARXMIS" description="Receive DMA Masked Interrupt Status" begin="16" end="16" width="1" rwaccess="R"/>
		<bitfield id="DMATXMIS" description="Transmit DMA Masked Interrupt Status" begin="17" end="17" width="1" rwaccess="R"/>
	</register>
	<register id="UARTICR" width="32" page="1" offset="0x44" internal="0" description="UART Interrupt Clear">
		<bitfield id="RXIC" description="Receive Interrupt Clear" begin="4" end="4" width="1" rwaccess="RW"/>
		<bitfield id="TXIC" description="Transmit Interrupt Clear" begin="5" end="5" width="1" rwaccess="RW"/>
		<bitfield id="RTIC" description="Receive Time-Out Interrupt Clear" begin="6" end="6" width="1" rwaccess="RW"/>
		<bitfield id="FEIC" description="Framing Error Interrupt Clear" begin="7" end="7" width="1" rwaccess="RW"/>
		<bitfield id="PEIC" description="Parity Error Interrupt Clear" begin="8" end="8" width="1" rwaccess="RW"/>
		<bitfield id="BEIC" description="Break Error Interrupt Clear" begin="9" end="9" width="1" rwaccess="RW"/>
		<bitfield id="OEIC" description="Overrun Error Interrupt Clear" begin="10" end="10" width="1" rwaccess="RW"/>
		<bitfield id="EOTIC" description="End of Transmission Interrupt Clear" begin="11" end="11" width="1" rwaccess="RW"/>
		<bitfield id="9BITIC" description="9-Bit Mode Interrupt Clear" begin="12" end="12" width="1" rwaccess="RW"/>
		<bitfield id="DMARXIC" description="Receive DMA Interrupt Clear" begin="16" end="16" width="1" rwaccess="RW"/>
		<bitfield id="DMATXIC" description="Transmit DMA Interrupt Clear" begin="17" end="17" width="1" rwaccess="RW"/>
	</register>
	<register id="UARTDMACTL" width="32" page="1" offset="0x48" internal="0" description="UART DMA Control">
		<bitfield id="RXDMAE" description="Receive DMA Enable" begin="0" end="0" width="1" rwaccess="RW"/>
		<bitfield id="TXDMAE" description="Transmit DMA Enable" begin="1" end="1" width="1" rwaccess="RW"/>
		<bitfield id="DMAERR" description="DMA on Error" begin="2" end="2" width="1" rwaccess="RW"/>
	</register>
	<register id="UART9BITADDR" width="32" page="1" offset="0xa4" internal="0" description="UART 9-Bit Self Address">
		<bitfield id="ADDR" description="Self Address for 9-Bit Mode" begin="7" end="0" width="8" rwaccess="RW"/>
		<bitfield id="9BITEN" description="Enable 9-Bit Mode" begin="15" end="15" width="1" rwaccess="RW"/>
	</register>
	<register id="UART9BITAMASK" width="32" page="1" offset="0xa8" internal="0" description="UART 9-Bit Self Address Mask">
		<bitfield id="MASK" description="Self Address Mask for 9-Bit Mode" begin="7" end="0" width="8" rwaccess="RW"/>
	</register>
	<register id="UARTPP" width="32" page="1" offset="0xfc0" internal="0" description="UART Peripheral Properties">
		<bitfield id="SC" description="Smart Card Support" begin="0" end="0" width="1" rwaccess="R"/>
		<bitfield id="NB" description="9-Bit Support" begin="1" end="1" width="1" rwaccess="R"/>
		<bitfield id="MS" description="Modem Support" begin="2" end="2" width="1" rwaccess="R"/>
		<bitfield id="MSE" description="Modem Support Extended" begin="3" end="3" width="1" rwaccess="R"/>
	</register>
	<register id="UARTPeriphID4" width="32" page="1" offset="0xfd0" internal="0" description="UART Peripheral Identification 4">
		<bitfield id="PID4" description="UART Peripheral ID Register [7:0]" begin="7" end="0" width="8" rwaccess="R"/>
	</register>
	<register id="UARTPeriphID5" width="32" page="1" offset="0xfd4" internal="0" description="UART Peripheral Identification 5">
		<bitfield id="PID5" description="UART Peripheral ID Register [15:8]" begin="7" end="0" width="8" rwaccess="R"/>
	</register>
	<register id="UARTPeriphID6" width="32" page="1" offset="0xfd8" internal="0" description="UART Peripheral Identification 6">
		<bitfield id="PID6" description="UART Peripheral ID Register [23:16]" begin="7" end="0" width="8" rwaccess="R"/>
	</register>
	<register id="UARTPeriphID7" width="32" page="1" offset="0xfdc" internal="0" description="UART Peripheral Identification 7">
		<bitfield id="PID7" description="UART Peripheral ID Register [31:24]" begin="7" end="0" width="8" rwaccess="R"/>
	</register>
	<register id="UARTPeriphID0" width="32" page="1" offset="0xfe0" internal="0" description="UART Peripheral Identification 0">
		<bitfield id="PID0" description="UART Peripheral ID Register [7:0]" begin="7" end="0" width="8" rwaccess="R"/>
	</register>
	<register id="UARTPeriphID1" width="32" page="1" offset="0xfe4" internal="0" description="UART Peripheral Identification 1">
		<bitfield id="PID1" description="UART Peripheral ID Register [15:8]" begin="7" end="0" width="8" rwaccess="R"/>
	</register>
	<register id="UARTPeriphID2" width="32" page="1" offset="0xfe8" internal="0" description="UART Peripheral Identification 2">
		<bitfield id="PID2" description="UART Peripheral ID Register [23:16]" begin="7" end="0" width="8" rwaccess="R"/>
	</register>
	<register id="UARTPeriphID3" width="32" page="1" offset="0xfec" internal="0" description="UART Peripheral Identification 3">
		<bitfield id="PID3" description="UART Peripheral ID Register [31:24]" begin="7" end="0" width="8" rwaccess="R"/>
	</register>
	<register id="UARTPCellID0" width="32" page="1" offset="0xff0" internal="0" description="UART PrimeCell Identification 0">
		<bitfield id="CID0" description="UART PrimeCell ID Register [7:0]" begin="7" end="0" width="8" rwaccess="R"/>
	</register>
	<register id="UARTPCellID1" width="32" page="1" offset="0xff4" internal="0" description="UART PrimeCell Identification 1">
		<bitfield id="CID1" description="UART PrimeCell ID Register [15:8]" begin="7" end="0" width="8" rwaccess="R"/>
	</register>
	<register id="UARTPCellID2" width="32" page="1" offset="0xff8" internal="0" description="UART PrimeCell Identification 2">
		<bitfield id="CID2" description="UART PrimeCell ID Register [23:16]" begin="7" end="0" width="8" rwaccess="R"/>
	</register>
	<register id="UARTPCellID3" width="32" page="1" offset="0xffc" internal="0" description="UART PrimeCell Identification 3">
		<bitfield id="CID3" description="UART PrimeCell ID Register [31:24]" begin="7" end="0" width="8" rwaccess="R"/>
	</register>
</module>