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TMS320F28335, power down sequencing requirement for XRS pin and VDD.

WENBO LI
Intellectual 440 points
Other Parts Discussed in Thread: TMS320F28335

From the data manual of TMS320F28335 (SPRS439H), there is a power sequencing described in section 6.8, copied below.

"During power down, the XRS pin must be pulled low at least 8 us

 

prior to VDD reaching 1.5 V. This is to enhance the flash reliability."

This requirement seems odd. Does anybody have any experience or any suggestions on this? Is there any application notes regarding this requirement? 

How this requirement is to implemented in the design? I wonder.

  • 0
    TI__Expert 8500 points

    Wenbo,

    You should be able to use a voltage supervisor to monitor VDDIO or VDD and make sure the caps on VDD are large enough that the voltage decay is slow enough for the supervisor to trip in time.

    Regards,
    Dave Foley

     

  • 0 in reply to David Foley
    Intellectual 440 points

    Dave,

    Thanks for your suggestions. But in principle, I don't understand how this timing will affect the flash reliability.

    Even when the VDD goes down to or below 1.5V and XRS/ pin still keeps high, the code that runs from the on-chip flash won't be able to erase the flash memory at all if the code doe not conduct any erase/write operations.

    In short, why the violation of this timing requirement will affect the reliablity of the flash memory? In which scenario it will affect?

    Thanks,

    Wenbo

  • 0 in reply to WENBO LI
    TI__Expert 8500 points

    Wenbo,

    It is not a matter of code executing and changing the flash, it is a matter of the behavior of the transistors in the flash circuit during low power operation.

    Regards,
    Dave Foley