TMS320F28388S: issue of using GPIO qualification for PWM EXTSYNCIN1

Strong ZHANG

Part Number: TMS320F28388S

HI Expert,

My customer are using two MCU for PWM sync up, mMCU generate EXSYNCCOUT event to sMCU which show as below waveform(purple waveform mMCU-GPIO37),

in sMCU, also use GPIO37 for PWM EXTSYNCIN1, and use GPIO3 for PWM EXSYNCCOUT just for test.

in both mMCU and sMCU, there will have PWM interrupt and use gpio to toggle to indicate when will the PWM ISR occur,

If use GPIO qualification mode for sMCU PWM EXTSYNCIN1 pin(GPIO37), then sMCU PWM ISR does not match with that of mMCU PWM ISR, which does not as expected.

but PWM EXSYNCCOUT in sMCU is correct and match with PWM EXTSYNCIN1 signal, only PWM ISR event is wrong.

If they did not use GPIO qualification mode for sMCU PWM EXTSYNCIN1 pin(GPIO37), then everything is ok.

could you suggest is it ok to use GPIO qualification for PWM EXTSYNCIN1? any suggestion for this issue?

over 4 years ago

0 Nima Eskandari over 4 years ago

TI__Guru 52040 points

Well your qualification will be delayed becuse depending on your GPIO qualification period, it will need to capture the input multiple times. The EXTSYNCOUT is also a VERY short signal. your GPIO qualificaion period will have a max value that if you go over, then you shouldnt have an output.

0 Strong ZHANG over 4 years ago in reply to Nima Eskandari

TI__Expert 4420 points

Hi Nima,

Thanks for your reply.

The signal that input for PWM EXTSYNCIN1 do have a very width pulse, not a very short signal, please see the purple waveform below which output from mMCU-GPIO37, and there is no problem for sMCU EXSYNCCOUT signal, only have problem for PWM ISR at sMCU.

0 Nima Eskandari over 4 years ago in reply to Strong ZHANG

TI__Guru 52040 points

What do you do do with your ISR, SET A GPIO at the beginning then clear at the end? Share the ISR code with me!

0 Strong ZHANG over 4 years ago in reply to Nima Eskandari

TI__Expert 4420 points

Hi Nima,

when enter the ISR, both MCU set GPIO59 to 0, and at the end set GPIO59 to 1.

0 Nima Eskandari over 4 years ago in reply to Strong ZHANG

TI__Guru 52040 points

Strong,

In that case it looks like the ISR is being executed on time but the duration is short. That's why I would like to see the content of the ISR.

Nima

0 Strong ZHANG over 4 years ago in reply to Nima Eskandari

TI__Expert 4420 points

Hi Nima,

The issue is that ISR occur twice in one PWM period, the ISR that below marked by green arrow should not occur. and did not match with the sMCU EXSYNCCOUT signal. any suggestion for this issue?

0 Nima Eskandari over 4 years ago in reply to Strong ZHANG

TI__Guru 52040 points

What are the sources of interrupt enabled? Also is the unwanted interrupts perfectly aligned with GPIO59? it looks like they are configured to be dependent.

Nima

0 Strong ZHANG over 4 years ago in reply to Nima Eskandari

TI__Expert 4420 points

Hi Nima,

they clear and set GPIO59 only in EPWM ISR, for more detail, please refer to the code that I sent to you.

0 Nima Eskandari over 4 years ago in reply to Strong ZHANG

TI__Guru 52040 points

Do you have interrupt nesting? Can you clear the ACK group flag at the end of the ISR?

Also please change the EPwm1Regs.ETSEL.bit.INTSEL = 3; to be "1" not "3".

When you have 3. you will get two interrupts per PWM cycle, in up-down mode.

0 Strong ZHANG over 4 years ago in reply to Nima Eskandari

TI__Expert 4420 points

Yes, they have interrupt nesting, but PWM interrupt have higher priority and can nest CAN interrupt.

at the end of PWM interrupt, there will clear ACK by using below code:

EPwm1Regs.ETCLR.bit.INT = 1;
PieCtrlRegs.PIEACK.all = PIEACK_GROUP3;

customer have change EPwm1Regs.ETSEL.bit.INTSEL = 3; from 3 to 1, but still have the issue.

It seem with the same setting, only remove the configure of GPIO qualification, then the issue resolved, any limitation for GPIO qualification in these use case?