TMDSECATCNCD379D: SPI CLK Frequency Calculate

What is the value that ends up in the BRR?

Hi, Gus:

Gus Martinez said:

What is the value that ends up in the BRR?

I didn't understand what you mean.

Sinan,
Thanks.

In your code you define SPI_BRR as a set of math calculations. The compiler will evaluate that math and the result will get written to the actual SPI register. I'm asking what is the value you see in BRR if you use CCS to view it during run time?

Hi, Gus:

The value I see in the BRR is "1" for 20 MHz.

Sinan.

The maximum SPI clock allowed is LSPCLK/4 per the device datasheet (see the "SPI Master Mode Timings" section in the device datasheet) and TRM ("SPIBRR Register" section). Therefore your setting of BRR=1 is not allowed. 

If you want to run the SPI clock at 20MHz, you will have to increase your LSPCLK setting. The LSPCLK max frequency is 200MHz when using an external clock source (see "Internal Clock Frequencies" section). A valid configuration would be to set LSPCLK=100MHz and the BRR=4. This would yield SPI clock = 100MHz / (4+1) = 20MHz.

Please review the setup and hold time requirements in the "SPI master mode timing requirements" section to determine if you will need to use the high-speed mode of the SPI to run at 20MHz. These really depends on the SPI slave device you are trying to communicate with.

Hi, Gus:

As you stated, I made the frequency settings for the 20 MHz signal as follows. But I couldn't get 20 MHz SPI CLK signal. As a result of the calculations you sent, the value I see in BRR is "0" for 20 MHz. When I equal the SPI_BRR variable to 4 directly, a 20 MHz signal is not generated (when SPI_BRR = 4).

#if CPU_FRQ_200MHZ
#define SPI_BRR        (100E6 / (4+1)) // 20 MHz CLK Signal
#endif

I read the "8.12.5.1.1 SPI Master Mode Timings" part in the TMS320F2837xD datasheet (page 165). According to the calculation above, a 20 MHz CLK signal should be generated.  

So where is the error? There may be errata status in datasheet or this DSP. 

Sinan,

Best regards.

As I previously mentioned, you need to change your LSPCLK configuration as well. Did you do that? What is the LSPCLK frequency? If you didn't change LSPCLK, likely it is still 25MHz (CPU freq/4). If you then set SPI_BRR to 20 (per your calculation), you will have a SPI CLK frequency of 1.19MHz (25MHz/21). Even if you set the SPI_BRR directly to 4, you will have a SPI CLK = 5 MHz (25MHz/5). 

Hi, Gus:

I made the LSPCLK configuration as follows. The LSPCLK frequency is 100 MHz. SPI_BRR variable is 4. However, it still didn't work.

//###########################################################################
//
// FILE:   Example_2837xDSpi_FFDLB.c
//
// TITLE:  SPI Digital Loop Back program.
//
//! \addtogroup cpu01_example_list
//! <h1>SPI Digital Loop Back (spi_loopback)</h1>
//!
//!  This program uses the internal loop back test mode of the peripheral.
//!  Other then boot mode pin configuration, no other hardware configuration
//!  is required. Interrupts are not used.
//!
//!  A stream of data is sent and then compared to the received stream.
//!  The sent data looks like this: \n
//!  0000 0001 0002 0003 0004 0005 0006 0007 .... FFFE FFFF \n
//!  This pattern is repeated forever.
//!
//!  \b Watch \b Variables \n
//!  - \b sdata - sent data
//!  - \b rdata - received data
//!
//
//###########################################################################
// $TI Release: F2837xD Support Library v3.12.00.00 $
// $Release Date: Fri Feb 12 19:03:23 IST 2021 $
// $Copyright:
// Copyright (C) 2013-2021 Texas Instruments Incorporated - http://www.ti.com/
//
// Redistribution and use in source and binary forms, with or without 
// modification, are permitted provided that the following conditions 
// are met:
// 
//   Redistributions of source code must retain the above copyright 
//   notice, this list of conditions and the following disclaimer.
// 
//   Redistributions in binary form must reproduce the above copyright
//   notice, this list of conditions and the following disclaimer in the 
//   documentation and/or other materials provided with the   
//   distribution.
// 
//   Neither the name of Texas Instruments Incorporated nor the names of
//   its contributors may be used to endorse or promote products derived
//   from this software without specific prior written permission.
// 
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 
// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 
// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 
// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 
// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 
// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
// $
//###########################################################################

//
// Included Files
//
#include "F28x_Project.h"

//
// Function Prototypes
//
void delay_loop(void);
void spi_xmit(Uint16 a);
void spi_fifo_init(void);
void spi_init(void);
void error(void);

void main(void)
{
   Uint16 sdata;  // send data
   Uint16 rdata;  // received data

//
// Step 1. Initialize System Control:
// PLL, WatchDog, enable Peripheral Clocks
// This example function is found in the F2837xD_SysCtrl.c file.
//
   InitSysCtrl();

//
// Step 2. Initialize GPIO:
// This example function is found in the F2837xD_Gpio.c file and
// illustrates how to set the GPIO to it's default state.
// Setup only the GP I/O only for SPI-A functionality
// This function is found in F2837xD_Spi.c
//
   InitSpiaGpio();

//
// Step 3. Clear all interrupts:
//
   DINT;

//
// Initialize PIE control registers to their default state.
// The default state is all PIE __interrupts disabled and flags
// are cleared.
// This function is found in the F2837xD_PieCtrl.c file.
//
   InitPieCtrl();

//
// Disable CPU __interrupts and clear all CPU __interrupt flags:
//
   IER = 0x0000;
   IFR = 0x0000;

//
// Initialize the PIE vector table with pointers to the shell Interrupt
// Service Routines (ISR).
// This will populate the entire table, even if the __interrupt
// is not used in this example.  This is useful for debug purposes.
// The shell ISR routines are found in F2837xD_DefaultIsr.c.
// This function is found in F2837xD_PieVect.c.
//
   InitPieVectTable();

   EALLOW;
   ClkCfgRegs.LOSPCP.bit.LSPCLKDIV = 1; // Set LSPCLK equal to SYSCLK/2 = 100 MHz
   EDIS;

//
// Step 4. Initialize the Device Peripherals:
//
   spi_fifo_init();     // Initialize the SPI FIFO

//
// Step 5. User specific code:
//
   sdata = 0xFFFF;
   //sdata = 0x0000;
   for(;;)
   {
        //
        // Transmit data
        //
        spi_xmit(sdata);

        //
        // Wait until data is received
        //
        while(SpiaRegs.SPIFFRX.bit.RXFFST !=1) { }

        //
        // Check against sent data
        //
        rdata = SpiaRegs.SPIRXBUF;
        if(rdata != sdata)
        {
            error();
        }
        sdata++;
   }
}

//
// delay_loop - Loop for a brief delay
//
void delay_loop()
{
    long i;
    for (i = 0; i < 1000000; i++) {}
}

//
// error - Error function that halts the debugger
//
void error(void)
{
    asm("     ESTOP0");     // Test failed!! Stop!
    for (;;);
}

//
// spi_xmit - Transmit value via SPI
//
void spi_xmit(Uint16 a)
{
    SpiaRegs.SPITXBUF = a;
}

//
// spi_fifo_init - Initialize SPIA FIFO
//
void spi_fifo_init()
{
    //
    // Initialize SPI FIFO registers
    //
    SpiaRegs.SPIFFTX.all = 0xE040;
    SpiaRegs.SPIFFRX.all = 0x2044;
    SpiaRegs.SPIFFCT.all = 0x0;

    //
    // Initialize core SPI registers
    //
    InitSpi();
}

//
// End of file
//

Can you edit the example below for 20 MHz?

C2000Ware_3_04_00_00\device_support\f2837xd\examples\cpu1\spi_loopback

Sinan,

Best regards.

Sorry, I do not have the same HW to try and SW modifications. 

What is the SPI CLK frequency you are seeing? 

Btw, the TMDSECATCNCD379D HW that you are using has a 25MHz crystal. The spi_loopback example programs the PLL to multiply the crystal frequency by either 20x or 10x. Have you adjusted those lines of code to make sure you are not running the CPU frequency out of spec?

In /spi_loopback_cpu01/Example_2837xDSpi_FFDLB.c

    //
    // Initialize the PLL control: SYSPLLMULT and SYSCLKDIVSEL.
    //
    // Defined options to be passed as arguments to this function are defined
    // in F2837xD_Examples.h.
    //
    // Note: The internal oscillator CANNOT be used as the PLL source if the
    // PLLSYSCLK is configured to frequencies above 194 MHz.
    //
    //  PLLSYSCLK = (XTAL_OSC) * (IMULT + FMULT) / (PLLSYSCLKDIV)
    //
#ifdef _LAUNCHXL_F28379D
    InitSysPll(XTAL_OSC,IMULT_40,FMULT_0,PLLCLK_BY_2);
#else
    InitSysPll(XTAL_OSC, IMULT_20, FMULT_0, PLLCLK_BY_2);
#endif // _LAUNCHXL_F28379D

Hi, Gus:

Gus Martinez said:

What is the SPI CLK frequency you are seeing? 

The SPI CLK frequency I see is 8 MHz.

Sinan,

Best regards.

Hi, Gus:

Gus Martinez said:

In /spi_loopback_cpu01/Example_2837xDSpi_FFDLB.c

I adjusted these lines of code to make sure I'm not running the CPU frequency out of spec.

Is there an errata in the TMDSECATCNCD379D product or the datasheet for this product?

I am waiting for your reply.

Sinan.

You can refer to the documents in the EVM product page.

www.ti.com/.../TMDSECATCNCD379D

There is a user guide for the board, no mention of any bugs.

www.ti.com/.../spruif9.pdf

What are the new PLL settings?

One correction to my earlier response. The EVM you should be using is the TMDSCNCD28379D controlCARD. That EVM has a 20MHz crystal on it. The example code should be setting the main clock to 20MHz x 20 / 2 = 200MHz which is within spec.

The documentation for the TMDSCNCD28379D is located at the link below.

https://www.ti.com/tool/TMDSCNCD28379D

The user guide for the EVM is located here:

https://www.ti.com/lit/ug/sprui76a/sprui76a.pdf

There is an errata for the board, but I don't see anything relating to SPI or input clock.

Please confirm you have the TMDSCNCD28379D controlCARD.

I got my hands on a TMDSCNCD28379D controlCARD. I modified the SPI loopback example code to run the SPI clock at 20MHz. Here are the changes I made.

#1 In file Example_2837xDSpi_FFDLB.c

//
// Step 1. Initialize System Control:
// PLL, WatchDog, enable Peripheral Clocks
// This example function is found in the F2837xD_SysCtrl.c file.
//
   InitSysCtrl();

   //Debug
   EALLOW;
   ClkCfgRegs.LOSPCP.bit.LSPCLKDIV = 1; // Set LSPCLK equal to SYSCLK/2 = 100 MHz
   EDIS;

#2 In file F2837xD_Spi.c

    // Enable master (0 == slave, 1 == master)
    // Enable transmission (Talk)
    // Clock phase (0 == normal, 1 == delayed)
    // SPI interrupts are disabled
    SpiaRegs.SPICTL.bit.MASTER_SLAVE = 1;
    SpiaRegs.SPICTL.bit.TALK = 1;
    SpiaRegs.SPICTL.bit.CLK_PHASE = 0;
    SpiaRegs.SPICTL.bit.SPIINTENA = 0;

    // Debug
    // Set the baud rate
    //SpiaRegs.SPIBRR.bit.SPI_BIT_RATE = SPI_BRR;
    SpiaRegs.SPIBRR.bit.SPI_BIT_RATE = 4;

#3 In file F2837xD_SysCtrl.c

#ifndef _FLASH
    //
    // Call Device_cal function when run using debugger
    // This function is called as part of the Boot code. The function is called
    // in the InitSysCtrl function since during debug time resets, the boot code
    // will not be executed and the gel script will reinitialize all the
    // registers and the calibrated values will be lost.
    //
    //Device_cal(); // Debug
#endif
#endif // CPU1

This last change shouldn't be needed. For some reason calling the Device_cal() function prevents the InitPeripheralClocks() function from being called. That is not expected. The InitPeripheralClocks() function is needed to turn on the SPIA module clock. Given that you had at least seen 8MHz SPI clock output, it seems you didn't have this problem. I will have to follow up on this internally.

Below is scope plot from GPIO18.

Part Number: TMDSECATCNCD379D

Hi, Dear TI Team:

I am using ENC28J60 ethernet LAN module with TMDSECATCNCD379D DSP in my project. The ENC28J60 chip uses the SPI peripheral. I am using the following example for SPI peripheral in DSP.

C:\ti\c2000\C2000Ware_3_04_00_00\device_support\f2837xd\examples\cpu1\spi_loopback

I have some questions for to you:

1. I changed the GPIO pins in the sample code. Are the changes I made correct?  (In the attached "F2837xD_Spi.c" file)
   
   
2. My SPI CLK frequency will be 20 MHz. For a 20 MHz CLK signal, LSPCLK = 100 MHz, SPIBRR = 4. But I couldn't get a 20 MHz CLK signal. (SPI Baud Rate = LSPCLK / (SPIBRR + 1)) (In the attached "F2837xD_Spi.c" file)
   
   
3. To test my SPI connection with the ENC28J60, I need to send and receive data to the ENC28J60 via SPI in DSP. However, I cannot get the initialize data specified in the ENC28J60 datasheet with SPI. Is there an error in my code for sending and receiving data with SPI?  DSP is the master device. ENC28J60 is the slave device. (In the attached "Example_2837xDSpi_FFDLB.c" file)

My files "F2837xD_Spi.c" and "Example_2837xDSpi_FFDLB.c" are attached.

/cfs-file/__key/communityserver-discussions-components-files/171/F2837xD_5F00_Spi.c

/cfs-file/__key/communityserver-discussions-components-files/171/Example_5F00_2837xDSpi_5F00_FFDLB.c

I have been trying to solve these problems for a long time. I need your help. I would be glad if to you help me.

Sinan,

Best regards.

Hi Sinan,

A SPI expert will be assigned and reply to you soon. I noticed you have another, related, post on-going: https://e2e.ti.com/support/microcontrollers/c2000-microcontrollers-group/c2000/f/c2000-microcontrollers-forum/1024915/tmdsecatcncd379d-spi-clk-frequency-calculate

Best,

Kevin

Hi, Kevin:

Kevin Allen18 said:

I noticed you have another, related, post on-going: https://e2e.ti.com/support/microcontrollers/c2000-microcontrollers-group/c2000/f/c2000-microcontrollers-forum/1024915/tmdsecatcncd379d-spi-clk-frequency-calculate

We couldn't solve the problem with "Gus Martinez".

I'm waiting for your answers.

Sinan.

Thanks and best regards.

Hi, Gus:

Gus Martinez said:

Please confirm you have the TMDSCNCD28379D controlCARD.

I have the TMDSCNCD28379D control board. But I am using TMDSECATCNCD379D development kit.

Sinan.

Hi, Gus:

I made the same changes in the example below, but I couldn't see a 20 MHz CLK signal.

C2000Ware_3_04_00_00\device_support\f2837xd\examples\cpu1\spi_loopback

Gus Martinez said:

Below is scope plot from GPIO18.

I can see 500 KHz SPI CLK signal on the oscilloscope screen.

Where could the problem be?

Sinan,

Thanks.

Hi, Gus:

Gus Martinez said:

What are the new PLL settings?

The LSPCLK frequency is 100 MHz. SPI_BRR variable is 4. Are there other CLK settings for SPI?

Sinan.

Thanks.

Sinan,

I am not sure what is going with your board. Are you sure you are running the .out you built after the changes were made? It is odd that you still see the 500kHz frequency (which is the default for the example code). Did you make any other changes to the code? Where are you probing for the SPI CLK?

You can also check the CPU registers after you load your code to make sure your changes are in fact taking effect. The SPI BRR register and the ClkCfgRegs.LOSPCP.bit.LSPCLKDIV bit would be two that I would check. If you can, provide screen shots of those registers.

One thing you can try is to load and run the .out that I compiled for the same project. I have attached it here. Full disclaimer: I was using the TMDSCNCD28379D control CARD + a TMDSHSECDOCK. I don't know if this can run as is with the TMDSECATCNCD379D attached to the controlCARD.

4024.spi_loopback_cpu01.zip

Sinan,

Apologies on the lack of reply on this thread from TI, Kevin had asked me to look into this post and getting the SPI expert looped in.  Given the other thread that Kevin mentions you already have ongoing with Gus I'm going to merge the two threads as this looks to be the same issue.  Gus has given a reply on the other thread earlier this AM, we can continue from there.

Best,

Matthew

Hi, Gus:

I successfully to get a 20 MHz SPI CLK signal. I'm grateful to you.

CLK signal for SPI does not occur in the following situation. For the CLK signal to work, the SPI send and receive commands must be inside the for(;;) loop. This is a very interesting situation indeed.

   spi_xmit(sdata);
   while(SpiaRegs.SPIFFRX.bit.RXFFST !=1) { }
   rdata = SpiaRegs.SPIRXBUF;

   for(;;)
   {
        /*
        //
        // Transmit data
        //
        spi_xmit(sdata);

        //
        // Wait until data is received
        //
        while(SpiaRegs.SPIFFRX.bit.RXFFST !=1) { }

        //
        // Check against sent data
        //
        rdata = SpiaRegs.SPIRXBUF;
        if(rdata != sdata)
        {
            error();
        }
        sdata++;*/
   }

My 20 MHz SPI CLK signal is as follows:

My CLK signal is not exactly a square wave. What could be the reason for this?

Sinan,

Thanks.

Hi, Gus:

The 20 MHz SPI CLK signal was required for the ENC28J60 Ethernet LAN module.

To test my SPI connection with the ENC28J60, I need to send and receive 8 bits of data to the ENC28J60 via SPI in the DSP. I made the necessary changes to my code. However, I cannot get the initialization data specified in the ENC28J60 datasheet via SPI. Is there a bug in my code to send and receive data with SPI? DSP is the master device. ENC28J60 is slave device.

My files "F2837xD_Spi.c" and "Example_2837xDSpi_FFDLB.c" are attached.

/cfs-file/__key/communityserver-discussions-components-files/171/6567.F2837xD_5F00_Spi.c

/cfs-file/__key/communityserver-discussions-components-files/171/0272.Example_5F00_2837xDSpi_5F00_FFDLB.c

Sinan,

Thanks.

Hi, Matthew:

Thank you for your feedbacks.

I will continue to solve the my problems I have with SPI peripheral with Gus. Gus patiently helps me. Gus is very knowledgeable. I am grateful to him and to you.

Sinan,

Thanks and best regards.

Hi Sinan,

Lots of questions here. I will try to address them all, but it is challenging give there are so many and answering each takes time. 

Sinan KAMILCELEBI said:

I successfully to get a 20 MHz SPI CLK signal. I'm grateful to you.

That's good to hear. Although you didn't mention if you figured out what was the problem.

Sinan KAMILCELEBI said:

CLK signal for SPI does not occur in the following situation. For the CLK signal to work, the SPI send and receive commands must be inside the for(;;) loop. This is a very interesting situation indeed.

EDIT (I corrected my questions after re-reading your post): This is not expected. Are you using a breakpoint at any point? The original example has SpiaRegs.SPIPRI.bit.FREE = 1. This should allow the SPI to continue operating even during a breakpoint. Can you confirm in CCS that this bit is set?

Sinan KAMILCELEBI said:

My CLK signal is not exactly a square wave. What could be the reason for this?

Fast clock, long wires, etc.

Sinan KAMILCELEBI said:

I changed the GPIO pins in the sample code. Are the changes I made correct?  (In the attached "F2837xD_Spi.c" file)

If you see the signals (CLK, MOSI, and STE) on the GPIO pins you need, then yes, they are correct. Let me know if you don't see toggling on the pins you need.

Sinan KAMILCELEBI said:

To test my SPI connection with the ENC28J60, I need to send and receive data to the ENC28J60 via SPI in DSP. However, I cannot get the initialize data specified in the ENC28J60 datasheet with SPI. Is there an error in my code for sending and receiving data with SPI?  DSP is the master device. ENC28J60 is the slave device. (In the attached "Example_2837xDSpi_FFDLB.c" file)

Unfortunately I am not going to be able to review your code and identify the issue (or issues) which are preventing you from achieving your goal. This shouldn't be the expectation. If you can simplify the problem and provide the right information, I will be better able to help you.

I suggest you figure out if there is an ID register or something similar in the ENC28J60. From there you can figure out what is the opcode you need to send and how many clocks you need to read the data. Look at the SPI signals on the bus and figure out if these are what you need to read that register. If they are not, please let me know where is the gap & we can go from there. 

Do you have a logic analyzer to better examine what the SPI is putting out? 

Hi, Gus:

Gus Martinez said:

Although you didn't mention if you figured out what was the problem.

I found and understood what the problem was. I explained what the problem was as follows. The situation I described below may be an bug of the 'spi_loopback' example.

Sinan KAMILCELEBI said:

CLK signal for SPI does not occur in the following situation. For the CLK signal to work, the SPI send and receive commands must be inside the for(;;) loop. This is a very interesting situation indeed.

Gus Martinez said:

Are you using a breakpoint at any point? The original example has SpiaRegs.SPIPRI.bit.FREE = 1. This should allow the SPI to continue operating even during a breakpoint. Can you confirm in CCS that this bit is set?

I'm not using a breakpoint at any point. I have 'SpiaRegs.SPIPRI.bit.FREE = 1' SPI breakpoint set in my program.

Gus Martinez said:

Let me know if you don't see toggling on the pins you need.

I changed the GPIO pin definitions for SPI. But, I can't see signals (CLK, MOSI and STE) on the GPIO pins I set below for SPI.

    //
    // Enable internal pull-up for the selected pins
    //
    // Pull-ups can be enabled or disabled by the user.
    // This will enable the pullups for the specified pins.
    // Comment out other unwanted lines.
    //

    GpioCtrlRegs.GPBPUD.bit.GPIO58 = 0; // Enable pull-up on GPIO58 (SPISIMOA)
    GpioCtrlRegs.GPBPUD.bit.GPIO59 = 0; // Enable pull-up on GPIO59 (SPISOMIA)
    GpioCtrlRegs.GPBPUD.bit.GPIO60 = 0; // Enable pull-up on GPIO60 (SPICLKA)
    GpioCtrlRegs.GPBPUD.bit.GPIO61 = 0; // Enable pull-up on GPIO61 (SPISTEA)


    //
    // Set qualification for selected pins to asynch only
    //
    // This will select asynch (no qualification) for the selected pins.
    // Comment out other unwanted lines.
    //

    GpioCtrlRegs.GPBQSEL2.bit.GPIO58 = 3; // Asynch input GPIO58 (SPISIMOA)
    GpioCtrlRegs.GPBQSEL2.bit.GPIO59 = 3; // Asynch input GPIO59 (SPISOMIA)
    GpioCtrlRegs.GPBQSEL2.bit.GPIO60 = 3; // Asynch input GPIO60 (SPICLKA)
    GpioCtrlRegs.GPBQSEL2.bit.GPIO61 = 3; // Asynch input GPIO61 (SPISTEA)

    //
    //Configure SPI-A pins using GPIO regs
    //
    // This specifies which of the possible GPIO pins will be SPI functional
    // pins.
    // Comment out other unwanted lines.
    //

    GpioCtrlRegs.GPBMUX2.bit.GPIO58 = 3; // Configure GPIO58 as SPISIMOA
    GpioCtrlRegs.GPBMUX2.bit.GPIO59 = 3; // Configure GPIO59as SPISOMIA
    GpioCtrlRegs.GPBMUX2.bit.GPIO60 = 3; // Configure GPIO60 as SPICLKA
    GpioCtrlRegs.GPBMUX2.bit.GPIO61 = 3; // Configure GPIO61 as SPISTEA

Gus Martinez said:

Do you have a logic analyzer to better examine what the SPI is putting out?

I have a logic analyzer to better examine what SPI peripheral reveals.

Thanks,

Sinan.

For the GPIO configuration, you also have to set the GPBGMUX2 registers. You can add these lines of code.

    //
    //Configure SPI-A pins using GPIO regs
    //
    // This specifies which of the possible GPIO pins will be SPI functional
    // pins.
    // Comment out other unwanted lines.
    //
	
	GpioCtrlRegs.GPBGMUX2.bit.GPIO58 = 3; // Configure GPIO58 as SPISIMOA
	GpioCtrlRegs.GPBGMUX2.bit.GPIO59 = 3; // Configure GPIO59 as SPISOMIA
	GpioCtrlRegs.GPBGMUX2.bit.GPIO60 = 3; // Configure GPIO60 as SPICLKA
	GpioCtrlRegs.GPBGMUX2.bit.GPIO61 = 3; // Configure GPIO61 as SPISTEA

	GpioCtrlRegs.GPBMUX2.bit.GPIO58 = 3; // Configure GPIO58 as SPISIMOA
	GpioCtrlRegs.GPBMUX2.bit.GPIO59 = 3; // Configure GPIO59as SPISOMIA
	GpioCtrlRegs.GPBMUX2.bit.GPIO60 = 3; // Configure GPIO60 as SPICLKA
	GpioCtrlRegs.GPBMUX2.bit.GPIO61 = 3; // Configure GPIO61 as SPISTEA

Hi, Gus:

Gus Martinez said:

For the GPIO configuration, you also have to set the GPBGMUX2 registers. You can add these lines of code.

I added the lines of code you specified. However, I could not get signal output from these GPIOs.

    //
    // Enable internal pull-up for the selected pins
    //
    // Pull-ups can be enabled or disabled by the user.
    // This will enable the pullups for the specified pins.
    // Comment out other unwanted lines.
    //

    GpioCtrlRegs.GPBPUD.bit.GPIO58 = 0; // Enable pull-up on GPIO58 (SPISIMOA)
    GpioCtrlRegs.GPBPUD.bit.GPIO59 = 0; // Enable pull-up on GPIO59 (SPISOMIA)
    GpioCtrlRegs.GPBPUD.bit.GPIO60 = 0; // Enable pull-up on GPIO60 (SPICLKA)
    GpioCtrlRegs.GPBPUD.bit.GPIO61 = 0; // Enable pull-up on GPIO61 (SPISTEA)

    //
    // Set qualification for selected pins to asynch only
    //
    // This will select asynch (no qualification) for the selected pins.
    // Comment out other unwanted lines.
    //

    GpioCtrlRegs.GPBQSEL2.bit.GPIO58 = 3; // Asynch input GPIO58 (SPISIMOA)
    GpioCtrlRegs.GPBQSEL2.bit.GPIO59 = 3; // Asynch input GPIO59 (SPISOMIA)
    GpioCtrlRegs.GPBQSEL2.bit.GPIO60 = 3; // Asynch input GPIO60 (SPICLKA)
    GpioCtrlRegs.GPBQSEL2.bit.GPIO61 = 3; // Asynch input GPIO61 (SPISTEA)

    //
    // Configure SPI-A pins using GPIO regs
    //
    // This specifies which of the possible GPIO pins will be SPI functional
    // pins.
    // Comment out other unwanted lines.
    //

    GpioCtrlRegs.GPBGMUX2.bit.GPIO58 = 3; // Configure GPIO58 as SPISIMOA
    GpioCtrlRegs.GPBGMUX2.bit.GPIO59 = 3; // Configure GPIO59 as SPISOMIA
    GpioCtrlRegs.GPBGMUX2.bit.GPIO60 = 3; // Configure GPIO60 as SPICLKA
    GpioCtrlRegs.GPBGMUX2.bit.GPIO61 = 3; // Configure GPIO61 as SPISTEA

    GpioCtrlRegs.GPBMUX2.bit.GPIO58 = 3; // Configure GPIO58 as SPISIMOA
    GpioCtrlRegs.GPBMUX2.bit.GPIO59 = 3; // Configure GPIO59 as SPISOMIA
    GpioCtrlRegs.GPBMUX2.bit.GPIO60 = 3; // Configure GPIO60 as SPICLKA
    GpioCtrlRegs.GPBMUX2.bit.GPIO61 = 3; // Configure GPIO61 as SPISTEA

Sinan.

I can try this on my end tomorrow in hardware.

Sinan,

Everything is working for me fine. There is something specific to your code or HW setup that is stopping your progress. Here is what I tried:

- Configure SPI CLK to 20MHz

- Configure pin mux to use GPIO58-GPIO61 for SPI (I actually used your code here)

- Modify SPI code to transmit one value outside for() loop. 

As mentioned before I used the C2000ware example code as a starting point with an F2837xD control card + docking station. 

C:\ti\c2000\C2000Ware_3_04_00_00\device_support\f2837xd\examples\cpu1\spi_loopback\cpu01\

The one additional thing I did is to add a call to InitPeripheralClocks() from main(). As I mentioned before, this was not being called correctly in the original example which causes the SPI module to not receive an internal clock and then nothing works. You do see data coming out of the SPI, so I don't believe this happens in your case.

I am attaching several source files here if you want to compare against what you have. I believe these are the only source files I modified. 

2728.e2e.zip

Hi, Gus:

Gus Martinez said:

As mentioned before I used the C2000ware example code as a starting point with an F2837xD control card + docking station.

I am using the same devices and SPI example as you. I don't use anything other than F2837xD control board + docking station.

20 MHz SPI CLK signal and new GPIO definitions (GPIO58-GPIO61) are working. But if I send and receive SPI data inside the for(;;) loop. It isn't working if SPI signals (MISO, MOSI, CLK, STEA) are used outside of the for(;;) loop.

I am trying to find this problem.

Sinan,

Good days,

Thanks and best regards.

Hi, Gus:

I tried many solutions over the weekend but couldn't solve this problem.

Gus Martinez said:

I am attaching several source files here if you want to compare against what you have. I believe these are the only source files I modified. 

2728.e2e.zip

It is very interesting that these codes do not work for me. 

What other way can we try to solve the problem?

Sinan,

Thanks.

Hi, Gus:

I am stopping the my code just before the spi_xmit() call. I also set up and calibrate an oscilloscope/logic analyzer. I then proceeding to run my code. But I am not getting any SPI signal (MOSI, CLK). 

However, when I put the SPI send function inside the for(;;) loop, SPI signals are generating immediately and I can see these signals on the oscilloscope and logic analyzer.

I've looked at all the SPI related posts in the Texas E2E design support. However, I could not find any information on this issue.

Thanks.

Sinan,

Can you upload both of your .out files (one with send function outside for() loop and one with send outside for() loop)? I can try running them & checking register configurations.

Hi, Gus:

Thank you very much for your feedbacks.

My problem is solved. I am thankful to you.

Gus Martinez said:

Could it be that you are not triggering your oscilloscope or logic analyzer correctly?

The problem is caused by the incorrect my oscilloscope trigger setting.

Gus Martinez said:

Can you upload both of your .out files (one with send function outside for() loop and one with send outside for() loop)?

I have uploaded both .out files. (one with send function outside of for(;;) loop and one with send out for(;;) loop)

/cfs-file/__key/communityserver-discussions-components-files/171/spi_5F00_loopback_5F00_cpu01_5F00_for_280029005F00_loop.zip

/cfs-file/__key/communityserver-discussions-components-files/171/spi_5F00_loopback_5F00_cpu01_5F00_outside_5F00_for_280029005F00_loop.zip

Sinan,

Thanks and best regards,
Good days.