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TMS320F280025: questions about how to set the interrupt priority

Lu Hang
Prodigy 225 points

Part Number: TMS320F280025

I set up two interrupt,CPU_Timer1 interrput of 100us and ADCA interrupt of 50us.I didn't cofigurate the interrupt priority.I find the CPU_Timer1 interrput  has a higher priority than ADCA interrupt.However,I want ADCA interrupt has a higher interrupt than CPU_Timer1 interrput。What code should I add to my interrupt to achieve my goal.

ADCA interrupt isr function:

__interrupt void adcA1ISR(void)
{

ADC_clearInterruptStatus(ADCA_BASE, ADC_INT_NUMBER1);

if(true == ADC_getInterruptOverflowStatus(ADCA_BASE, ADC_INT_NUMBER1))
{
ADC_clearInterruptOverflowStatus(ADCA_BASE, ADC_INT_NUMBER1);
ADC_clearInterruptStatus(ADCA_BASE, ADC_INT_NUMBER1);
}

Interrupt_clearACKGroup(INTERRUPT_ACK_GROUP1);

}

CPU_Timer1 interrput:

__interrupt void cpuTimer1ISR(void)
{

  Interrupt_clearACKGroup(INTERRUPT_ACK_GROUP1);

}

I tried to modify my code according to demo code:"interrupt_ex2_sw_prioritization",the modfied code is as following:

ADCA interrupt isr function:

__interrupt void adcA1ISR(void)
{
volatile uint16_t tempPIEIER = HWREGH(PIECTRL_BASE + PIE_O_IER1);
IER |= M_INT1;
IER &= MINT1;
HWREGH(PIECTRL_BASE + PIE_O_IER1) &= MG1_7;

Interrupt_clearACKGroup(0xFFFFU);
__asm(" NOP");
EINT;

ADC_clearInterruptStatus(ADCA_BASE, ADC_INT_NUMBER1);

if(true == ADC_getInterruptOverflowStatus(ADCA_BASE, ADC_INT_NUMBER1))
{
ADC_clearInterruptOverflowStatus(ADCA_BASE, ADC_INT_NUMBER1);
ADC_clearInterruptStatus(ADCA_BASE, ADC_INT_NUMBER1);

Interrupt_clearACKGroup(INTERRUPT_ACK_GROUP1);

DINT;
HWREGH(PIECTRL_BASE + PIE_O_IER1) = tempPIEIER;

}

CPU_Timer1 interrput:

__interrupt void cpuTimer1ISR(void)
{
IER &= MINT13;
EINT;


Interrupt_clearACKGroup(INTERRUPT_ACK_GROUP1);

DINT;
}

What mistakes did I make?I would appreciate that if you can help me to modify my code?

  • 0
    TI__Mastermind 19795 points

    Hi,

    Thanks for your question! If I understand correctly, you are wanting to have ADCA interrupt with higher PRIORITY than CPU TIMER1, correct?

    This is actually the case by default. ADCA1 interrupt is part of "PIE Group 1", which is actually INT1 line. The only higher priority interrupt than this group is "Reset".

    CPU TIMER1 Interrupt is on the "INT13" line. The entire PIE module (meaning all peripheral interrupts) have higher priority than CPU TIMER1.

    Please see the "CPU Interrupt Vectors" table in the Technical Reference Manual (linked here) for a full list of the interrupt vectors and their priority.

    So to summarize you do not need to add any IER modifications to the interrupt routine. In fact, you can enter and exit both ISR's normally.

    I hope that helps (and simplifies) your project!

    Regards!

    Vince

  • 0 in reply to Vince
    Prodigy 225 points

    Thank you very much.You are right.Sorry,I made a mistake about understanding the interrupt priority.It is due to that there is a remainder operation in my cpu timer interrupt and it cost too much time.So period of ADCA1 interrupt is not steady because of the long time application in Cputimer1.So if I want ADCA1 interrupt to break cpu timer interrupt to reach the purpose of interrupt nesting.How do I modify my code to make  interrupt nesting true?

  • 0 in reply to Lu Hang
    TI__Mastermind 19795 points

    Hi,

    Thanks for the follow up! That makes sense what you are trying to do. We have a great guide on this at the following link location. This walks through all the steps needed to nest the interrupts into one another.

    https://software-dl.ti.com/C2000/docs/c28x_interrupt_nesting/html/index.html#example-code

    Note that you will likely have an easier time than the examples because you don't need to change priority, only allow nesting.

    So it should likely just require in the CPU timer interrupt:

    (1) save the PIEIER register at the beginning (likely optional)

    (2) Set the IER|= ### to allow ADCA's group to be allowed to run

    (3) normal ISR code

    (4) Restore the PIEIER register (likely optional)

    You should not need to change the PIEIER what you have described!

    Regards,

    Vince

  • 0 in reply to Vince
    Prodigy 225 points

    Hi Vince:

         I have add code into my CPUTimer1 Interrupt function，It seemed that interrupt nesting has been made true.However,I still have some confusion.

         If I disabe the CPUTimer1 interrupt,the time gap between two adjacent ADCA Interrupts is nearly 5000 as following:

         

        

        If I enable the CPUTimer1 interrupt but not let ADCA interrupt break CPUTimer1,and the code in CPUTimer1 cost about 38us,The "xx_gap" means time gap between two adjacent interrupt,"xx_gap2" means the time cost of application in interrupt.

        

            

          If I enable the CPUTimer1 interrupt and also let ADCA interrupt to be able to break CPUTimer1,the time gap is as following:

         

          

          It seemed that interrupt nesting had made effects,but the time gap between two ADCA interrupt function is not accurate nearly 50us.Does the the progress of CPUTimer1 interrupt service turning to  ADCA interrupt service take up some time? 

  • 0 in reply to Lu Hang
    TI__Mastermind 19795 points

    Hi,

    Thanks for the follow-up!

    Lu Hang said:
    Does the the progress of CPUTimer1 interrupt service turning to  ADCA interrupt service take up some time? 

    Yes, the time to enter each interrupt takes up some time so this can be what you are seeing (although it does look a little high). This can vary widely dependent on if there are pipeline delays due to wait-stated memory, RPT instructions, multiple-cycle instructions, etc.

    Assuming there are no sources of delay like the ones mentioned above, the minimum number of cycles for just the internal context savings can go up to 32 cycles (taking into account the minimum 14 cycles + 8 fixed-point pushes + 10 floating-point pushes). At 20 MHz frequency, this would be ~1.6 us MINIMUM time for EVERY context switch. This can go much higher depending on the items I mentioned previously like wait-stated memory.

    When your ADC interrupt nests inside the CPU_Timer1 interrupt, it may see the context switch time as the CPU_Timer1 items are saved.

    So to summarize, the answer to your question is that the context switch from CPUTimer1 to ADCA interrupt does take time.

    Regards,

    Vince