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TMS320F28388D: Question about ADC Trigger

Green Deng
Expert 4490 points

Part Number: TMS320F28388D

Dear team:

ADC_setupSOC(ADCA_BASE, ADC_SOC_NUMBER0, ADC_TRIGGER_EPWM1_SOCA,ADC_CH_ADCIN0, 63);
ADC_setupSOC(ADCA_BASE, ADC_SOC_NUMBER1, ADC_TRIGGER_EPWM1_SOCA,ADC_CH_ADCIN1, 63);
ADC_setupSOC(ADCA_BASE, ADC_SOC_NUMBER2, ADC_TRIGGER_EPWM1_SOCA,ADC_CH_ADCIN2, 63);
ADC_setupSOC(ADCA_BASE, ADC_SOC_NUMBER3, ADC_TRIGGER_EPWM1_SOCA,ADC_CH_ADCIN3, 63);
ADC_setupSOC(ADCA_BASE, ADC_SOC_NUMBER4, ADC_TRIGGER_EPWM1_SOCA,ADC_CH_ADCIN4, 63);
ADC_setupSOC(ADCA_BASE, ADC_SOC_NUMBER5, ADC_TRIGGER_EPWM1_SOCA,ADC_CH_ADCIN5, 63);
ADC_setupSOC(ADCA_BASE, ADC_SOC_NUMBER6, ADC_TRIGGER_EPWM1_SOCA,ADC_CH_ADCIN14, 63);
ADC_setupSOC(ADCA_BASE, ADC_SOC_NUMBER7, ADC_TRIGGER_EPWM1_SOCA,ADC_CH_ADCIN15, 63);

PWM up-count mode, Trigger ADC sampling when TBCTR = PRD:  "ADC_setInterruptPulseMode(ADCA_BASE, ADC_PULSE_END_OF_CONV);"

An interrupt is triggered after sampling is completed:

ADC_setInterruptSource(ADCA_BASE, ADC_INT_NUMBER1, ADC_SOC_NUMBER7); It is measured that it takes 7US from PWM trigger ADC sampling to entry interrupt.

ADC_setInterruptSource(ADCA_BASE, ADC_INT_NUMBER1, ADC_SOC_NUMBER0); It is measured that it takes 1US from PWM trigger ADC sampling to entry interrupt.

Is this time difference because SOC0-15 is refreshed sequentially, so if ADC_SOC_NUMBER7 is used to trigger the interrupt sampling data, then 0-7 are all collected. If it is ADC_SOC_NUMBER1 to trigger, ADC_SOC_NUMBER7 may not be completed yet, and the data read is the last time?

If this is the case, pwm triggers the ADC interrupt for more than 7us. So when the switching frequency is above 120K, will the interrupt frequency be limited by 7us?

Best regards

  • 0
    TI__Guru 60865 points

    Hi Green,

    I think your understanding is correct:

    • You'll generally want to trigger the ISR after all conversions in the sequence are complete. 
      • So for a sequence of conversions from SOC0 to SOC7, the safest thing to do would be to trigger the ISR after SOC7, otherwise you might read some stale data
      • You can try to factor in the ISR context switch time and any calculations that occur before the ADC results are read.  For instance, if the results for SOC0 to SOC3 get used separately from the results for SOC4 to SOC7, you might be able to enter the ISR a little early.  Consider that entering the ISR and processing results 0 to 3 takes 1us, then you could enter the ISR after SOC6 (1 us early) and still read fresh results when the ISR gets around to reading results 4 to 7.  
    • If the ADC is operating in 16-bit mode, the maximum sample rate is about 1MSPS therefore the conversion time is about 1us (but you can get exact times from the timing information in the datasheet - see the "ADC Timing Diagrams" section). 
      • If SOC0 to SOC7 are all triggered in a sequence and the ADC is using 16-bit mode, then SOC0 will be done after about 1us and SOC7 will be done after about 8us
      • This time will limit how fast you can trigger the ISR (8us period is indeed about 125 kHz frequency)
      • However, note that this device has 4 ADCs which are intended to be used in parallel, so if you need 8 total 16-bit resolution conversions you should be using 4 ADCs in parallel to produce the results in about 2 us, which will give a much faster maximum ePWM trigger rate.