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TIDM-1000: PWM signals diagram in Build1 (dutyPU_DC)

Part Number: TIDM-1000
Other Parts Discussed in Thread: TIDM-1007

How should PWM signals look like in default setting (duty cycle = 0.5) on all channels? All 6 PWMs should be triggering at the same time or all of them should be triggered in round robin like way?

Could someone briefly draw a diagram of them for all three phases?

  • Hi Pawel,

    You should see all 6 PWM behave the same under build 1 when setting the same duty cycle. 

    VIENNA_HAL_setupPWM is the function to setup PWM output. The PWM counter of three phases are synced and there is no phase shift. So each phase will calculate its own duty cycle and CMPA etc when the loop is closed.

    You can refer to the code for more details.

    Regards,

    Chen

  • Adding more background to the original question. I'm running Build 1 and confirming all the values and functioning of the board.

    Voltage sensing has been calibrated and is working correctly for all three phases. Looking on the graphs all three sine and all three currents are looking like in the UG.

    Before running the build I disabled three transistors drivers to be absolutely safe, using DISABLE pin.

    When I get to the 6.4.1.5 point 8 of the UG it says to set dutyPU_DC to 0.5 and clearTrip to 1.

    Looking on the oscilloscope I see each PWM going to the driver and being driven simultaneously. In other words both driver outputs are getting opened at the same time.

    Is it correct?

    User Guide's figure 4 shows that each driver channel, should be opened exclusively, so in lower sine one should be driven and then the other in the upper sine.

  • Hi Pawel,

    You observation is correct. 

    Please see the comments on the right side of Figure 4:

    Though Q1 and Q2 are shown to be not switching here for understanding, the current flow does not change even when it is switched(this is how we implemented). SW for TIDM-1007 switches the FETs synchronously with each other

    Regards,

    Chen