Hi
Ti,
How do I use GS ram for two different cores using the same source file and linker file also avoiding memory contention between both?
Is there a way to determine the core id at compile time to use in the source file, cmd file?
as an exapmle we want in the following way
#if defined(__TI_EABI__)
isrfunc : LOAD = RAMD0 | RAMLS0 | RAMLS1 | RAMLS2 | RAMLS3 | RAMLS4,
if(core1 cpu)
RUN = RAMGS15,
LOAD_START(isrfuncLoadStart),
LOAD_END(isrfuncLoadEnd),
RUN_START(isrfuncRunStart),
LOAD_SIZE(isrfuncLoadSize)
if(core2 cpu)
RUN = RAMGS14,
LOAD_START(isrfuncLoadStart),
LOAD_END(isrfuncLoadEnd),
RUN_START(isrfuncRunStart),
LOAD_SIZE(isrfuncLoadSize)
endif
or can we define like this __TI_EABI__ macro for the core as well?
Thanks
Harshit
