Part Number: TMS320F28379D
Hi,
I am using F28379D to run my three phase grid connected inverter. But I keep on facing memory issues in CCS whenever I add something in the code. I am not doing anything fancy in the code.
Whenever I try to implement a filter (Low pass filter) or even some close loop control, it gives me the following error i.e., 'program will not fit into available memory. placement with alignment/blocking fails for section ".text" size 0x1e9b page 0. Available memory ranges: 2837xD_RAM_lnk_cpu1.cmd /SVPWM_1 line 53 C/C++ Problem ' (screenshot and code attached).
// The Low Pass Filter Code
#define EMATH_OneOrderLpf(in, out, wT) \
out += (wT) * ( (in) - (out) );
I am also attaching the optimization settings of my program. If I make the optimization setting to global optimization, I no longer see the error but code stops working in the debug stage. Please advise if I am not doing the setting correctly or do I need to change any other settings to make my code run.
// main File
//###########################################################################
//
// FILE: control_cpu01.c
//
// TITLE: Inverter Control (SVPWM)
//
//!
//!
//!
//###########################################################################
//
// Included Files
#define MATH_TYPE FLOAT_MATH //IQ_MATH
#include "IQmathLib.h"
#include <math.h>
#include "F28x_Project.h"
#include "settings.h"
#include "Solar_F.h"
//#include "Solar_IQ.h"
// Create an instance of DATALOG Module
//DLOG_4CH_F dlog_4ch1;
// Create an instance of PLL Module
SPLL_3ph_SRF_F spll1;
//SPLL_3ph_SRF_IQ spll1;
//SPLL_1ph_SOGI_F spll2;
// Create an instance of ABCtoDQ module
ABC_DQ0_POS_F abc_dq0_pos1;
iCLARKE_F iclark;
// Function Prototypes
void InitEPwm(void);
void ConfigureADC(void);
__interrupt void epwm1_isr(void);
__interrupt void adca1_isr(void);
Uint16 usRunState;
Uint16 usFaultFlag;
Uint16 usResumePWM;
Uint16 usPwmPeriod;
Uint16 EPwm1_DB;
Uint16 EPwm2_DB;
Uint16 EPwm3_DB;
Uint16 usPhase;
Uint16 usPwm2Phase;
Uint16 usPwm3Phase;
Uint16 EPwm1_CMP;
Uint16 EPwm2_CMP;
Uint16 EPwm3_CMP;
float32 fDutyCycle;
float32 fDutyCycle1;
float32 fDutyCycle2;
float32 fDutyCycle3;
float32 fTdb;
float32 fTdb2;
float32 fTdb3;
Uint16 TestPwm;
float32 Maximum;
float32 Minimum;
float32 fUma;
float32 fUmb;
float32 fUmc;
float32 fUmz;
float32 fUmax;
float32 fUmin;
float32 fUmaxAbs;
float32 fUminAbs;
float32 fUmodA;
float32 fUmodB;
float32 fUmodC;
float32 fUmodAlpha;
float32 fUmodBeta;
Uint16 usCmpValA;
Uint16 usCmpValB;
Uint16 usCmpValC;
//Uint16 usCmpVal1;
//Uint16 usCmpVal2;
//Uint16 usCmpVal3;
float32 fMI240;
float32 fVpert;
float32 fVout1;
float32 fIdc1;
float32 fIpert;
// ADC values
float32 fVan1;
float32 fVan2;
float32 fVbn;
float32 fVbn1;
float32 fVbn2;
float32 fVcn1;
float32 fVcn2;
float32 fIa;
float32 fIb;
float32 fIc;
float32 fVin;
float32 fIinv;
float32 fIinvFLT;
float32 fVinvab;
float32 fVinvbc;
float32 fVinvca;
float32 fVinvbc1;
float32 fkbc;
float32 fVab;
float32 fVbc;
float32 fVca;
float32 fVabAbs;
float32 fVbcAbs;
float32 fVcaAbs;
float32 fVout;
float32 fVoutFlt;
float32 fIdc;
float32 fIindA;
float32 fIindB;
float32 fIindC;
float32 fIdcFlt;
float32 fWTLpfIind;
float32 fIindAFlt;
float32 fIindBFlt;
float32 fIindCFlt;
float32 fIerrA;
float32 fIerrB;
float32 fIerrC;
float32 fCurrentFaultDc;
float32 fCurrentFaultA;
float32 fCurrentFaultB;
float32 fCurrentFaultC;
float32 fOver_Current;
float32 fOver_Voltage;
float32 fVoutFault;
float32 fIindFlt;
float32 fWTLpfIind;
float32 fIrefMag;
float32 fIrefLimit;
float32 fIset;
float32 fSlope;
float32 fVdc_ref1;
float32 fVdc_ref2;
float32 fVslope;
float32 fVoltageRefRamp;
float32 fVdcPeak1;
float32 fVdcPeak2;
float32 fIref1;
float32 fIref2;
float32 fIslope;
float32 fVdc;
float32 fVdcPeak;
float32 fVdcPeakNom;
float32 fVdcRef;
float32 fVdcref_grid;
float32 fVdcref_gridFLT;
float32 fVan2FLT;
float32 fVbn2FLT;
float32 fVcn2FLT;
float32 fVin;
float32 fVinFlt;
float32 fVerr;
float32 fKp2;
float32 fKi2;
float32 fInt2;
float32 fVoltCtrl;
float32 fKp;
float32 fKi;
float32 fCurrentRef;
float32 fIerrA;
float32 fIerrB;
float32 fIerrC;
float32 fIntA;
float32 fIntB;
float32 fIntC;
float32 fCurrCtrlA;
float32 fCurrCtrlB;
float32 fCurrCtrlC;
float32 fIref;
float32 fIerr;
float32 fInt;
float32 fCurrCtrl;
float32 fVoltageRef;
float32 fVerr;
float32 fVoltCtrl;
float32 fScale1;
float32 fScale2;
float32 fScale3;
float32 fScale4;
float32 fOffset1;
float32 fOffset2;
float32 fOffset3;
float32 fOffset4;
float32 fgainVo;
float32 foffsetVo;
float32 fgainVin;
float32 foffsetVin;
float32 fgainIdc;
float32 foffsetIdc;
float32 fgainIindC;
float32 foffsetIindC;
float32 fgainIindB;
float32 foffsetIindB;
float32 fgainIindA;
float32 foffsetIindA;
float32 fIaOffset;
float32 fIaOffset2;
float32 fIagain1;
float32 fIagain2;
float32 fIbOffset;
float32 fIbOffset2;
float32 fIbgain1;
float32 fIbgain2;
float32 fIcOffset;
float32 fIcOffset2;
float32 fIcgain1;
float32 fIcgain2;
float32 fgainVan1;
float32 fgainVan2;
float32 foffsetVan1;
float32 foffsetVan2;
float32 fgainVbn1;
float32 fgainVbn2;
float32 foffsetVbn1;
float32 foffsetVbn2;
float32 fgainVbn;
float32 foffsetVbn;
float32 fgainVcn1;
float32 fgainVcn2;
float32 foffsetVcn1;
float32 foffsetVcn2;
float32 fka;
float32 fkb;
float32 fkc;
float32 fgainVin;
float32 foffsetVin;
float32 fgainIinv;
float32 foffsetIinv;
float32 fgainVinvab;
float32 foffsetVinvab;
float32 fgainVinvbc;
float32 foffsetVinvbc;
float32 fgainVinvca;
float32 foffsetVinvca;
float32 fVinvab_abs;
float32 fVinvbc_abs;
float32 fVinvca_abs;
float32 Vdcref_inv;
float32 fVab_grid;
float32 fVbc_grid;
float32 fVca_grid;
float32 fSineA;
float32 fSineB;
float32 fSineC;
float32 fSineAB;
float32 fSineBC;
float32 fSineCA;
float32 fThetaA;
float32 fThetaB;
float32 fThetaC;
float32 fThetaAB;
float32 fThetaBC;
float32 fThetaCA;
float32 fPhaseComp;
float32 fThetaModA;
float32 fThetaModB;
float32 fRelaya;
float32 fRelayb;
float32 fRelayc;
float32 GridConnect;
float32 fNormalize;
float32 FLTQs;
//float32 fDBCompThres;
//float32 fDBCompCoeff;
//float32 fDBCompA;
//float32 fDBCompB;
//float32 fDBCompC;
//float32 fVmagSq;
//float32 fVmag;
//float32 fVmagFlt;
//float32 fVmagFltWt;
// Variables for viewing signals in CCS graph
#define RESULTS_BUFFER_SIZE 128
int16 Adc1[RESULTS_BUFFER_SIZE];
int16 Adc2[RESULTS_BUFFER_SIZE];
int16 Adc3[RESULTS_BUFFER_SIZE];
int16 Adc4[RESULTS_BUFFER_SIZE];
//int16 Adc5[RESULTS_BUFFER_SIZE];
//int16 Adc6[RESULTS_BUFFER_SIZE];
//int16 Adc7[RESULTS_BUFFER_SIZE];
//int16 Adc8[RESULTS_BUFFER_SIZE];
Uint16 resultsIndex;
Uint16 saveIndex;
volatile Uint16 bufferFull;
Uint16 usStartSaveData;
Uint16 samplePace;
// ****************************************************************************
// Variables for MACROS
// ****************************************************************************
float32 T = 1.0/PWM_FREQUENCY; // Samping period (sec), see parameter.h
_iq VdTesting = _IQ(1.0), // Vd reference (pu)
VqTesting = _IQ(0.0), // Vq reference (pu)
IdRef = _IQ(0.0), // Id reference (pu)
IqRef = _IQ(0.0), // Iq reference (pu)
SpeedRef = _IQ(1.0), // For Closed Loop tests
lsw1Speed = _IQ(0.02); // initial force rotation speed in search of QEP index pulse
// Instance a few transform objects (ICLARKE is added into SVGEN module)
//CLARKE clarke1 = CLARKE_DEFAULTS;
//PARK park1 = PARK_DEFAULTS;
IPARK ipark1 = IPARK_DEFAULTS;
//PHASEVOLTAGE volt1 = PHASEVOLTAGE_DEFAULTS;
// Instance a Space Vector PWM modulator. This modulator generates a, b and c
// phases based on the d and q stationery reference frame inputs
//SVGENDPWM_240 svgen1 = SVGENDPWM_240_DEFAULTS;
SVGEN svgen1 = SVGEN_DEFAULTS;
// Instance a ramp controller to smoothly ramp the frequency
RMPCNTL rc1 = RMPCNTL_DEFAULTS;
// Instance a ramp(sawtooth) generator to simulate an Anglele
RAMPGEN rg1 = RAMPGEN_DEFAULTS;
CLARKE clarke1 = CLARKE_DEFAULTS;
PARK park1 = PARK_M_DEFAULTS;
// ****************************************************************************
// Variables for Datalog module
// ****************************************************************************
//float DBUFF_4CH1[100],
// DBUFF_4CH2[100],
// DBUFF_4CH3[50],
// DBUFF_4CH4[50],
// DlogCh1,
// DlogCh2,
// DlogCh3,
// DlogCh4;
void Shutdown(void);
//
// Main
//
void main(void)
{
InitSysCtrl();
CpuSysRegs.PCLKCR2.bit.EPWM1 = 1;
CpuSysRegs.PCLKCR2.bit.EPWM2 = 1;
CpuSysRegs.PCLKCR2.bit.EPWM3 = 1;
CpuSysRegs.PCLKCR2.bit.EPWM7 = 1;
CpuSysRegs.PCLKCR2.bit.EPWM8 = 1;
CpuSysRegs.PCLKCR2.bit.EPWM9 = 1;
InitEPwm1Gpio();
InitEPwm2Gpio();
InitEPwm3Gpio();
InitEPwm7Gpio();
InitEPwm8Gpio();
InitEPwm9Gpio();
// EALLOW;
// GpioCtrlRegs.GPAMUX1.bit.GPIO4 = 0; // GPIO
// GpioCtrlRegs.GPAMUX1.bit.GPIO6 = 0; // GPIO
// GpioCtrlRegs.GPADIR.bit.GPIO4 = 1; // output
// GpioCtrlRegs.GPADIR.bit.GPIO6 = 1; // output
// EDIS;
DINT;
InitPieCtrl();
IER = 0x0000;
IFR = 0x0000;
InitPieVectTable();
//
// Interrupts that are used in this example are re-mapped to
// ISR functions found within this file.
//
EALLOW; // This is needed to write to EALLOW protected registers
PieVectTable.EPWM1_INT = &epwm1_isr;
PieVectTable.ADCA1_INT = &adca1_isr; //function for ADCA interrupt 1
EDIS; // This is needed to disable write to EALLOW protected registers
// Configure the ADC and power it up
// Setup the ADC for ePWM triggered conversions
// ************ SHOULD BE DONE BEFORE PWM CONFIG **************
ConfigureADC();
//
// Step 4. Initialize the Device Peripherals:
//
EALLOW;
CpuSysRegs.PCLKCR0.bit.TBCLKSYNC =0;
EDIS;
InitEPwm();
EALLOW;
CpuSysRegs.PCLKCR0.bit.TBCLKSYNC =1;
EDIS;
//
// Step 5. User specific code
// Initialize variables
usRunState = 0;
usResumePWM = 0;
fOver_Current = 49.0;
fOver_Voltage = 800.0;
fMI240 = 1.0;
// fVmagFltWt = TWO_PI * 1.0 * SAMPLING_PERIOD; // 1 Hz LPF
fPhaseComp = 0.0;
fVdcPeakNom = 2.2;
fVinFlt = 100.0;
fVdcPeak = 0; //200.0;
fWTLpfIind = TWO_PI * 1000.0 * SAMPLING_PERIOD; // 1 kHz LPF
fKp = 0.02;
fKi = 20.0;
fKp2 = 0.2;
fKi2 = 30.0;
// fOffset1 = 3.6;
// fScale1 = 312.0;
// fScale2 = 533.3;
// fScale3 = 533.3;
// fScale4 = 1.0;
// fOffset1 = -35.0;
// fOffset2 = -814.0;
// fOffset3 = -818.0;
// fOffset4 = -1;
rg1.StepAngleMax = _IQ(GRID_FREQ * SAMPLING_PERIOD);
// SPLL_3ph_SRF_F_init(GRID_FREQ, SAMPLING_PERIOD, &spll1);
// Kp = 166.6;
// Ki = 27755.55;
// T = 1/10e3;
// B0 = (2*Kp + Ki*T)/2
// B1 = -(2*Kp - Ki*T)/2
// SPLL_1ph_SOGI_F_init(GRID_FREQ,((float)(SAMPLING_PERIOD)), &spll2);
// SPLL_1ph_SOGI_F_coeff_update(((float)(SAMPLING_PERIOD)), (float)(TWO_PI*GRID_FREQ), &spll2);
SPLL_3ph_SRF_F_init(GRID_FREQ, SAMPLING_PERIOD, &spll1);
fNormalize = 0.1;
spll1.lpf_coeff.B0_lf = 223.4194;
spll1.lpf_coeff.B1_lf = -220.901;
// ****************************************************
// Initialize DATALOG module
// ****************************************************
// DLOG_4CH_F_init(&dlog_4ch1);
// dlog_4ch1.input_ptr1 = &DlogCh1; //data value
// dlog_4ch1.input_ptr2 = &DlogCh2;
// dlog_4ch1.input_ptr3 = &DlogCh3;
// dlog_4ch1.input_ptr4 = &DlogCh4;
// dlog_4ch1.output_ptr1 = &DBUFF_4CH1[0];
// dlog_4ch1.output_ptr2 = &DBUFF_4CH2[0];
// dlog_4ch1.output_ptr3 = &DBUFF_4CH3[0];
// dlog_4ch1.output_ptr4 = &DBUFF_4CH4[0];
// dlog_4ch1.size = 200;
// dlog_4ch1.pre_scalar = 5;
// dlog_4ch1.trig_value = 0.01;
// dlog_4ch1.status = 2;
for(resultsIndex = 0; resultsIndex < RESULTS_BUFFER_SIZE; resultsIndex++)
{
Adc1[resultsIndex] = 0;
Adc2[resultsIndex] = 0;
Adc3[resultsIndex] = 0;
Adc4[resultsIndex] = 0;
}
resultsIndex = 0;
saveIndex = 0;
bufferFull = 0;
samplePace = 2; // Rounding( F_sample / F_fundamental / BufferSize )
usStartSaveData = 0;
//DC-DC Converter
fgainVo = 345.423;
foffsetVo = 0;
fgainVin = 172.7115;
foffsetVin = 0;
fgainIdc = 103.1;
fgainIindC = 108.7;
fgainIindB = 142.5;
fgainIindA = 142.5;
foffsetIdc = 1.502; //1.507;
foffsetIindC = 1.505; //1.507;
foffsetIindB = 1.502; //1.506;
foffsetIindA = 1.502; //1.506;
//Grid Currents
fIaOffset = 2.222;
fIagain1 = -2;
fIagain2 = 15.5;
fIaOffset2 = 0.00484;;//-0.0118;
fIbOffset = 2.222;
fIbgain1 = -2;
fIbgain2 = 15.5;
fIbOffset2 = 0.006452;// 0.00484;//-0.0118;
fIcOffset = 2.222;
fIcgain1 = -2;
fIcgain2 = 15.5;
fIcOffset2 = -0.0118;
//Grid Voltages
fgainVan1 = -2;
foffsetVan1 = 2.25;
fgainVan2 = 181;
foffsetVan2 = 0.125;
fgainVbn1 = -2;
foffsetVbn1 = 2.25;
fgainVbn2 = 181;
foffsetVbn2 = 0.125;
fgainVcn1 = -2;
foffsetVcn1 = 2.25;
fgainVcn2 = 181;
foffsetVcn2 = 0.125;//0.125;
// Inverter Voltages
foffsetVinvab = 1.5;
foffsetVinvbc = 1.494;
foffsetVinvca = 1.5;
fgainVinvab = -1000;
fgainVinvbc = -1000;
fgainVinvca = -1000;
//
// Inverter Current
foffsetIinv = 1.502;
fgainIinv = 285;//142.5;
// Enable CPU INT3 which is connected to EPWM1-3 INT:
//
// IER |= M_INT3;
IER |= M_INT1; // for ADC isr
EINT; // Enable Global interrupt INTM
ERTM; // Enable Global realtime interrupt DBGM
//
// Enable PIE interrupt
//
// PieCtrlRegs.PIEIER3.bit.INTx1 = 1; // PWM
PieCtrlRegs.PIEIER1.bit.INTx1 = 1; // ADC isr
// conv_duty();
for(;;)
{
asm (" NOP");
}
}
//
// epwm1_isr - EPWM1 ISR
//
__interrupt void epwm1_isr(void)
{
// GpioDataRegs.GPASET.bit.GPIO8 = 1; // Pin 57
asm (" NOP"); asm (" NOP");
asm (" NOP"); asm (" NOP");
asm (" NOP"); asm (" NOP");
asm (" NOP"); asm (" NOP");
asm (" NOP"); asm (" NOP");
// EPwm2Regs.TBPHS.bit.TBPHS = usPwm2Phase;
// EPwm3Regs.TBPHS.bit.TBPHS = usPwm3Phase;
// EPwm1Regs.TBPRD = usPwmPeriod;
// EPwm2Regs.TBPRD = usPwmPeriod;
// EPwm3Regs.TBPRD = usPwmPeriod;
// GpioDataRegs.GPACLEAR.bit.GPIO8 = 1;
// Clear INT flag for this timer
EPwm1Regs.ETCLR.bit.INT = 1;
// Acknowledge this interrupt to receive more interrupts from group 3
PieCtrlRegs.PIEACK.all = PIEACK_GROUP3;
}
//
// adca1_isr - Read ADC Buffer in ISR
//
__interrupt void adca1_isr(void)
{
// GpioDataRegs.GPASET.bit.GPIO8 = 1; //Pin 5 of J3 (PWM 5A)
//**********************************************
// Get ADC Results
//**********************************************
// 1000V => 3.0V
// fVout = ((float32)AdcaResultRegs.ADCRESULT0 * 0.0007326007326) * 360.0 + fOffset2;
// fIdc = ((float32)AdcaResultRegs.ADCRESULT1 * 0.0007326007326 - 1.65) * 91.5 + fOffset1;
// fIindC = ((float32)AdcaResultRegs.ADCRESULT2 * 0.0007326007326 - 1.65) * 91.5 + fOffset1;
// fIindB = ((float32)AdcaResultRegs.ADCRESULT3 * 0.0007326007326 - 1.65) * 91.5 + fOffset1;
// fIindA = ((float32)AdcaResultRegs.ADCRESULT4 * 0.0007326007326 - 1.65) * 91.5 + fOffset1;
// Sensor HLSR 50-SM/SP33, datasheet sensitivity 9.2mV/A (108.7 A/V)
// Current signals, sampled bias 1.63V,
/* fIdc = ((float32)AdcaResultRegs.ADCRESULT1 * 0.0007326007326 - 1.63) * 108.7;
fIindC = ((float32)AdcaResultRegs.ADCRESULT2 * 0.0007326007326 - 1.63) * 108.7;
fIindB = ((float32)AdcaResultRegs.ADCRESULT3 * 0.0007326007326 - 1.63) * 108.7;
fIindA = ((float32)AdcaResultRegs.ADCRESULT4 * 0.0007326007326 - 1.63) * 108.7;*/
//
// EMATH_OneOrderLpf(fVout, fVoutFlt, fWTLpfIind);
// EMATH_OneOrderLpf(fIindA, fIindAFlt, fWTLpfIind);
// EMATH_OneOrderLpf(fIindB, fIindBFlt, fWTLpfIind);
// EMATH_OneOrderLpf(fIindC, fIindCFlt, fWTLpfIind);
// fVab = fScale2 * (((float32)AdcaResultRegs.ADCRESULT0) * 0.0007326007326) + fOffset2;
// fVa = fScale2 * (((float32)AdcaResultRegs.ADCRESULT6) * 0.0007326007326) + fOffset2;
// fVb = fScale3 * (((float32)AdcaResultRegs.ADCRESULT7) * 0.0007326007326) + fOffset3;
// fVc = fScale4 * (((float32)AdcaResultRegs.ADCRESULT3) * 0.0007326007326 + fOffset4);
// fVc = 0.0 - fVa - fVb;
// EMATH_OneOrderLpf(fVin, fVinFlt, fVmagFltWt);
// New PCB
fVout = ((float32)AdcaResultRegs.ADCRESULT0 * 0.0007326007326) * fgainVo + foffsetVo;
fIdc = ((float32)AdcaResultRegs.ADCRESULT1 * 0.0007326007326 - foffsetIdc) * (-1*fgainIdc); //108.7 1.504
fIindC = ((float32)AdcaResultRegs.ADCRESULT2 * 0.0007326007326 - foffsetIindC) * fgainIindC; //95.54
fIindB = ((float32)AdcaResultRegs.ADCRESULT3 * 0.0007326007326 - foffsetIindB) * fgainIindB; //108.7
fIindA = ((float32)AdcaResultRegs.ADCRESULT4 * 0.0007326007326 - foffsetIindA) * fgainIindA; //108.7
fIa = ((((float32)AdcbResultRegs.ADCRESULT0 * 0.0007326007326 - fIaOffset ) * fIagain1)) * fIagain2;
fIb = ((((float32)AdcbResultRegs.ADCRESULT1 * 0.0007326007326 - fIbOffset ) * fIbgain1)) * fIbgain2;
fIc = ((((float32)AdcbResultRegs.ADCRESULT2 * 0.0007326007326 - fIcOffset ) * fIcgain1)) * fIcgain2;
// fVan = ((((float32)AdcbResultRegs.ADCRESULT3 * 0.0007326007326) * fgainVan1) * fgainVan2) + foffsetVan;
fVan1 = ((float32)AdcbResultRegs.ADCRESULT3 * 0.0007326007326 - foffsetVan1) * fgainVan1; //op-amp
fVan2 = ((fVan1 - foffsetVan2) * fgainVan2) + fka; //LEM
fVbn1 = ((float32)AdcbResultRegs.ADCRESULT4 * 0.0007326007326 - foffsetVbn1) * fgainVbn1;
fVbn2 = ((fVbn1 - foffsetVbn2) * fgainVbn2) + fkb;
fVcn1 = ((float32)AdcbResultRegs.ADCRESULT5 * 0.0007326007326 - foffsetVcn1) * fgainVcn1;
// fVcn2 = ((fVcn1 - foffsetVcn2) * fgainVcn2) + fkc;
fVcn2 = - fVan2 - fVbn2;
fVab_grid =fVan2-fVbn2;
fVbc_grid =fVbn2-fVcn2;
fVca_grid =fVcn2-fVan2;
/* EMATH_OneOrderLpf(fVan2, fVan2FLT, fWTLpfIind);
EMATH_OneOrderLpf(fVbn2, fVbn2FLT, fWTLpfIind);
EMATH_OneOrderLpf(fVcn2, fVcn2FLT, fWTLpfIind);*/
Maximum = MAX_THREE(fVan2,fVbn2,fVcn2);
Minimum = MIN_THREE(fVan2,fVbn2,fVcn2);
fVdcref_grid = Maximum - Minimum;
EMATH_OneOrderLpf(fVdcref_grid, fVdcref_gridFLT, fWTLpfIind);
// Input Voltage
fVin = ((float32)AdcdResultRegs.ADCRESULT0 * 0.0007326007326) * fgainVin + foffsetVin;
// Inverter Current
// fIinv = ((float32)AdcdResultRegs.ADCRESULT1 * 0.0007326007326 - foffsetIinv) * fgainIinv;
// EMATH_OneOrderLpf(fIinv, fIinvFLT, fWTLpfIind);
// Inverter Output Voltages
fVinvab = (((float32)AdcdResultRegs.ADCRESULT2 * 0.0007326007326) - foffsetVinvab) * fgainVinvab;
fVinvbc = (((float32)AdcdResultRegs.ADCRESULT3 * 0.0007326007326) - foffsetVinvbc) * fgainVinvbc;
fVinvca = (((float32)AdcdResultRegs.ADCRESULT4 * 0.0007326007326) - foffsetVinvca) * fgainVinvca;
fRelaya = ABS(fVinvab - fVab_grid);
fRelayb = ABS(fVinvbc - fVbc_grid);
fRelayc = ABS(fVinvca - fVca_grid);
/*
if ((fRelaya < 10) & (fRelayb < 10) & (fRelayc < 10)) GridConnect = 1;
if(GridConnect == 0){GpioDataRegs.GPBCLEAR.bit.GPIO34 = 1;} //Relay off
else {GpioDataRegs.GPBSET.bit.GPIO34 = 1;} //Relay on
*/
/* if(GridConnect == 0){GpioDataRegs.GPBCLEAR.bit.GPIO34 = 1;} //Relay off
else {GpioDataRegs.GPBSET.bit.GPIO34 = 1;} //Relay on*/
if(GridConnect == 0){ GpioDataRegs.GPACLEAR.bit.GPIO8 = 1;} //Relay off
else { GpioDataRegs.GPASET.bit.GPIO8 = 1;} //Relay on
#if 0
spll2.u[0] = fVab * fNormalize; // fNormalize = 0.1 gives good result
SPLL_1ph_SOGI_F_MACRO(spll2);
EMATH_OneOrderLpf(-spll2.u_D[0]*10.0, fVmagFlt, fVmagFltWt);
UP_DOWN_LIMIT(fVmagFlt, 900.0, 1.0);
fThetaAB = spll2.theta[1] + (fPhaseComp * TWO_PI);
if( fThetaAB > TWO_PI ) { fThetaAB = fThetaAB - TWO_PI; }
fThetaBC = fThetaAB + FOUR_PI_DIV3;
if( fThetaBC > TWO_PI ) { fThetaBC = fThetaBC - TWO_PI; }
fThetaCA = fThetaAB + TWO_PI_DIV3;
if( fThetaCA > TWO_PI ) { fThetaCA = fThetaCA - TWO_PI; }
fSineAB = spll2.__relaxed_sin * SQRT_THREE;
fSineBC = sin(fThetaBC) * SQRT_THREE;
fSineCA = sin(fThetaCA) * SQRT_THREE;
fSineA = (fSineAB - fSineCA)*0.333333;
fSineB = (fSineBC - fSineAB)*0.333333;
fSineC = (fSineCA - fSineBC)*0.333333;
fUmodAlpha = fSineA;
fUmodBeta = (fSineA + 2.0 * fSineB) * 0.57735026918963;
fVabAbs = ABS(fSineAB);
fVbcAbs = ABS(fSineBC);
fVcaAbs = ABS(fSineCA);
fVdc = MAX_THREE(fVabAbs, fVbcAbs, fVcaAbs);
UP_DOWN_LIMIT(fVdc, 1.733, 0.1);
fMI240 = 1.7320508 / fVdc * VdTesting;
UP_DOWN_LIMIT(fMI240, 1.154, 0.5);
#endif
// // if( spll2.__relaxed_sin > 0 )
// if( fSineA > 0 )
// {
// GpioDataRegs.GPASET.bit.GPIO4 = 1;
// }
// else
// {
// GpioDataRegs.GPACLEAR.bit.GPIO4 = 1;
// }
//
// if( fSineC > 0 )
// {
// GpioDataRegs.GPASET.bit.GPIO6 = 1;
// }
// else
// {
// GpioDataRegs.GPACLEAR.bit.GPIO6 = 1;
// }
//If measuring va,vb and vc, use this part of code
// ------------------------------------------------------------------------------
// Measure phase currents, subtract the offset and normalize from (-0.5,+0.5) to (-1,+1).
// Connect inputs of the CLARKE module and call the clarke transformation macro
// ------------------------------------------------------------------------------
// clarke1.As = fVa; // Phase A Voltage
// clarke1.Bs = fVb; // Phase B Voltage
// clarke1.Cs = fVc; // Phase C Voltage
// CLARKE_MACRO(clarke1)
// fVmagSq = (clarke1.Alpha)*(clarke1.Alpha) + (clarke1.Beta)*(clarke1.Beta);
// fVmag = sqrt(fVmagSq); // * 1.732050807;
// EMATH_OneOrderLpf(fVmag, fVmagFlt, fVmagFltWt);
#if 0
abc_dq0_pos1.a = fVa;
abc_dq0_pos1.b = fVb;
abc_dq0_pos1.c = fVc;
abc_dq0_pos1.sin = -sin((spll1.theta[1]));
abc_dq0_pos1.cos = -cos((spll1.theta[1]));
ABC_DQ0_POS_F_MACRO(abc_dq0_pos1);
//spll1.v_q[0] = (abc_dq0_pos1.d) * fNormalize; // / abc_dq0_pos1.d);
spll1.v_q[0] = (abc_dq0_pos1.d) / fVmagFlt * fNormalize ;
SPLL_3ph_SRF_F_MACRO(spll1); // takes less time
#endif
// ------------------------------------------------------------------------------
// Connect inputs of the RMP module and call the ramp control macro
// ------------------------------------------------------------------------------
rc1.TargetValue = SpeedRef;
RC_MACRO(rc1)
// ------------------------------------------------------------------------------
// Connect inputs of the RAMP GEN module and call the ramp generator macro
// ------------------------------------------------------------------------------
rg1.Freq = rc1.SetpointValue;
RG_MACRO(rg1)
// Calculate Duty for Boost converter
fThetaA = rg1.Out * TWO_PI;
fThetaB = fThetaA + FOUR_PI_DIV3;
if( fThetaB > TWO_PI ) { fThetaB = fThetaB - TWO_PI; }
fThetaC = fThetaA + TWO_PI_DIV3;
if( fThetaC > TWO_PI ) { fThetaC = fThetaC - TWO_PI; }
fSineA = sin(fThetaA);
fSineB = sin(fThetaB);
fSineC = sin(fThetaC);
fSineAB = (fSineA - fSineB);
fSineBC = (fSineB - fSineC);
fSineCA = (fSineC - fSineA);
fVabAbs = ABS(fSineAB);
fVbcAbs = ABS(fSineBC);
fVcaAbs = ABS(fSineCA);
fVdc = MAX_THREE(fVabAbs, fVbcAbs, fVcaAbs);
UP_DOWN_LIMIT(fVdc, 1.733, 0.1);
fMI240 = 1.7320508 / fVdc;
UP_DOWN_LIMIT(fMI240, 1.154, 0.5);
//Connecting phase currents with Clark Macro
clarke1.As = fVan2; //fIaNorm; // Phase A curr.
clarke1.Bs = fVbn2;
//clarke1.Cs = fVbn2;//fIbNorm; // Phase B curr.
CLARKE_MACRO(clarke1)
// ------------------------------------------------------------------------------
// Connect inputs of the PARK module and call the park trans. macro
// ------------------------------------------------------------------------------
park1.Alpha = clarke1.Alpha;
park1.Beta = clarke1.Beta;
park1.Angle = rg1.Out;
park1.Sine = __sinpuf32(park1.Angle);
park1.Cosine = __cospuf32(park1.Angle);
PARK_M_MACRO(park1)
EMATH_OneOrderLpf(park1.Qs, FLTQs, fWTLpfIind);
spll1.v_q[0] = FLTQs*fNormalize;//0;
SPLL_3ph_SRF_F_MACRO(spll1);
// fThetaModA = fThetaA + fPhaseComp * TWO_PI;
// if( fThetaModA > TWO_PI ) { fThetaModA = fThetaModA - TWO_PI; }
// fThetaModB = fThetaModA + FOUR_PI_DIV3;
// if( fThetaModB > TWO_PI ) { fThetaModB = fThetaModB - TWO_PI; }
// fUmodAlpha = sin(fThetaModA);
// fUmodBeta = (sin(fThetaModA) + 2.0 * sin(fThetaModB)) * 0.57735026918963;
fUmodAlpha = fSineA;
fUmodBeta = (fSineA + 2.0 * fSineB) * 0.57735026918963;
#if 0
// ------------------------------------------------------------------------------
// Connect inputs of the PARK module and call the park trans. macro
// ------------------------------------------------------------------------------
park1.Alpha = clarke1.Alpha;
park1.Beta = clarke1.Beta;
// park1.Angle = rg1.Out;
park1.Angle = spll1.theta[1];
park1.Sine = __sinpuf32(park1.Angle);
park1.Cosine = __cospuf32(park1.Angle);
PARK_MACRO(park1)
spll1.v_q[0] = park1.Ds * fNormalize;
SPLL_3ph_SRF_F_MACRO(spll1);
// ------------------------------------------------------------------------------
// Connect inputs of the INV_PARK module and call the inverse park trans. macro
// There are two option for trigonometric functions:
// IQ sin/cos look-up table provides 512 discrete sin and cos points in Q30 format
// IQsin/cos PU functions interpolate the data in the lookup table yielding higher resolution.
// ------------------------------------------------------------------------------
ipark1.Ds = park1.Ds;//VdTesting;
ipark1.Qs = park1.Qs;//VqTesting;
// ipark1.Sine = __sinpuf32(rg1.Out);
// ipark1.Cosine = __cospuf32(rg1.Out);
// ipark1.Sine=_IQsinPU(rg1.Out);
// ipark1.Cosine=_IQcosPU(rg1.Out);
ipark1.Sine=__sinpuf32(rg1.Out);
ipark1.Cosine=__cospuf32(rg1.Out);
IPARK_MACRO(ipark1)
#endif
// //For open loop testing
// ipark1.Ds = VdTesting;
// ipark1.Qs = VqTesting;
//
// park1.Angle = rg1.Out;
// park1.Sine = __sinpuf32(park1.Angle);
// park1.Cosine = __cospuf32(park1.Angle);
//
// ipark1.Sine=park1.Sine;
// ipark1.Cosine=park1.Cosine;
// IPARK_MACRO(ipark1)
// ------------------------------------------------------------------------------
// Connect inputs of the SVGEN module and call the space-vector gen. macro
// ------------------------------------------------------------------------------
// svgen1.Ualpha = ipark1.Alpha;
// svgen1.Ubeta = ipark1.Beta;
svgen1.Ualpha = fUmodAlpha * VdTesting;
svgen1.Ubeta = fUmodBeta * VdTesting;
// svgen1.Ualpha = fUmodAlpha * fMI240;
// svgen1.Ubeta = fUmodBeta * fMI240;
/* // DPWM 1 (clamp at peak)
fUma = ipark1.Alpha;
fUmb = 0.5*( 1.732050807 * ipark1.Beta - ipark1.Alpha);
fUmc = 0.5*(-1.732050807 * ipark1.Beta - ipark1.Alpha);
fUmax = MAX_THREE(fUma, fUmb, fUmc);
fUmin = MIN_THREE(fUma, fUmb, fUmc);
fUmaxAbs = ABS(fUmax);
fUminAbs = ABS(fUmin);
if( fUmaxAbs > fUminAbs )
{
fUmz = 1.0 - fUmax;
}
else
{
fUmz = -1.0 - fUmin;
}
fUmodA = fUma + fUmz;
fUmodB = fUmb + fUmz;
fUmodC = fUmc + fUmz;
*/
//240CPWM
SVGENDPWM_240_MACRO(svgen1)
fUmodA = -svgen1.Ta;
fUmodB = -svgen1.Tb;
fUmodC = -svgen1.Tc;
// SVGENDPWM_MACRO(svgen1)
// SVGENDQ_MACRO(svgen1)
// fUmodA = svgen1.Ta;
// fUmodB = svgen1.Tb;
// fUmodC = svgen1.Tc;
// if( fVaAbs > fDBCompThres )
// {
// fDBCompA = fDBCompCoeff;
// }
//
// if( fVbAbs > fDBCompThres )
// {
// fDBCompB = fDBCompCoeff;
// }
//
// if( fVcAbs > fDBCompThres )
// {
// fDBCompC = fDBCompCoeff;
// }
//
// fUmodA = fUmodA * fDBCompA;
// fUmodB = fUmodB * fDBCompB;
// fUmodC = fUmodC * fDBCompC;
usCmpValA = (INV_PWM_HALF_TBPRD * fUmodA) + INV_PWM_HALF_TBPRD;
usCmpValB = (INV_PWM_HALF_TBPRD * fUmodB) + INV_PWM_HALF_TBPRD;
usCmpValC = (INV_PWM_HALF_TBPRD * fUmodC) + INV_PWM_HALF_TBPRD;
UP_DOWN_LIMIT(usCmpValA, INV_PWM_TBPRD, 0);
UP_DOWN_LIMIT(usCmpValB, INV_PWM_TBPRD, 0);
UP_DOWN_LIMIT(usCmpValC, INV_PWM_TBPRD, 0);
EPwm7Regs.CMPA.bit.CMPA = usCmpValA; //phase A
EPwm8Regs.CMPA.bit.CMPA = usCmpValB; //phase B
EPwm9Regs.CMPA.bit.CMPA = usCmpValC; //phase C
//
// usCmpVal1 = (Uint16)(fDutyCycle * (float32)CONTROL_TBPRD); // Duty for Top switch
//// usCmpVal2 = (Uint16)(fDutyCycle * (float32)CONTROL_TBPRD);
//// usCmpVal3 = (Uint16)(fDutyCycle * (float32)CONTROL_TBPRD);
//
// UP_DOWN_LIMIT(usCmpVal1, CONTROL_TBPRD, 5);
//
// EPwm1Regs.CMPA.bit.CMPA = usCmpVal1;
// EPwm2Regs.CMPA.bit.CMPA = usCmpVal1;
// EPwm3Regs.CMPA.bit.CMPA = usCmpVal1;
if( (ACTIVE == usRunState) && (NORMAL == usFaultFlag) )
{
if( usResumePWM )
{
// only need to change here for enabling/disabling phases
EALLOW;
GpioCtrlRegs.GPAMUX1.bit.GPIO0 = 1;
GpioCtrlRegs.GPAMUX1.bit.GPIO1 = 1;
GpioCtrlRegs.GPAMUX1.bit.GPIO2 = 1;
GpioCtrlRegs.GPAMUX1.bit.GPIO3 = 1;
GpioCtrlRegs.GPAMUX1.bit.GPIO4 = 1;
GpioCtrlRegs.GPAMUX1.bit.GPIO5 = 1;
EDIS;
usResumePWM = 0;
}
if( (fOver_Current <= ABS(fIdc) ) ||
(fOver_Current <= ABS(fIindA)) ||
(fOver_Current <= ABS(fIindB)) ||
(fOver_Current <= ABS(fIindC)) )
{
Shutdown();
fCurrentFaultDc = fIdc;
fCurrentFaultA = fIindA;
fCurrentFaultB = fIindB;
fCurrentFaultC = fIindC;
usFaultFlag = OVER_CURRENT;
}
if( fOver_Voltage <= ABS(fVout) )
{
Shutdown();
fVoutFault = fVout;
usFaultFlag = OVER_VOLTAGE;
}
/*
//For Ramp in fVdcPeak
if (fVdcPeak2 > fVdcPeak1)
{
fVdcPeak1 += fVslope;
}
else if (fVdcPeak2 < fVdcPeak1)
{
fVdcPeak1 -= fVslope;
}
else
{
fVdcPeak1 = fVdcPeak2;
}
fVdcPeak = fVdcPeak1;
*/
// fVdcPeak = fVdcPeak + 0.00005;
UP_DOWN_LIMIT(fVdcPeak, 800, 0.0);
// Both Open and Close Loop Controls
fVdcRef = fVdc * SQRT_THREE_RECIP * fVdcPeak;
UP_DOWN_LIMIT(fVdcRef, 1000.0, 20.0);
//OPEN LOOP CONTROL
fDutyCycle = fVinFlt / fVdcRef; // for top switch
// fDutyCycle = fDutyCycle1 + fVpert;
//CLOSE LOOP CONTROL
// Type-3 V/d Controller with/without Predictor
/*
GpioDataRegs.GPASET.bit.GPIO8 = 1;
fVoltageRef = fVdcRef;
fVerr = fVoltageRef - fVout;
fVoltCtrl = Vout_Controller_Predictor(fVerr); // Vout_control_type_three
UP_DOWN_LIMIT(fVoltCtrl, 0.7, 0.3);
fDutyCycle = 1.0 - fVoltCtrl;
GpioDataRegs.GPACLEAR.bit.GPIO8 = 1;
*/
/*
// Dual Loop Control
// k-factor Vout/Iin controller
fVoltageRef = fVdcRef;
fVerr = fVoltageRef - fVout;
fVoltCtrl = Vout_control(fVerr);
UP_DOWN_LIMIT(fVoltCtrl, 40, 0);
fIref = fVoltCtrl;
// k-factor Iin/d controller
fCurrentRef = fIref;
fIerr = fCurrentRef - fIdc;
fCurrCtrl = Iin_control(fIerr);
UP_DOWN_LIMIT(fCurrCtrl, 0.7, 0.2);
fDutyCycle = 1.0 - fCurrCtrl;
*/
// Both Open and Close Loop Controls
UP_DOWN_LIMIT(fDutyCycle,0.7,0.2);
fDutyCycle2 = fDutyCycle;
fDutyCycle3 = fDutyCycle;
EPwm1_CMP = (Uint16)(fDutyCycle * (0.5 * (float32)DC_DC_CONTROL_TBPRD));
EPwm2_CMP = (Uint16)(fDutyCycle2 * (0.5 * (float32)DC_DC_CONTROL_TBPRD));
EPwm3_CMP = (Uint16)(fDutyCycle3 * (0.5 * (float32)DC_DC_CONTROL_TBPRD));
EPwm1Regs.CMPA.bit.CMPA = EPwm1_CMP; // Phase A Main
EPwm2Regs.CMPA.bit.CMPA = EPwm2_CMP; // Phase B Main
EPwm3Regs.CMPA.bit.CMPA = EPwm3_CMP; // Phase C Main
}
else
{
Shutdown();
}
// EPwm1_DB = (Uint16)(fTdb * 0.1);
// EPwm11Regs.DBFED.bit.DBFED = EPwm1_DB;
// EPwm12Regs.DBFED.bit.DBFED = EPwm1_DB;
// EPwm9Regs.DBFED.bit.DBFED = EPwm1_DB;
// // Connect inputs of the DATALOG module
// DlogCh1 = svgen1.Ta;
// DlogCh2 = svgen1.Tb;
// DlogCh3 = svgen1.Tc;
// DlogCh4 = DlogCh2 - DlogCh3;
// // ------------------------------------------------------------------------------
// // Call the DATALOG update function.
// // ------------------------------------------------------------------------------
// DLOG_4CH_F_FUNC(&dlog_4ch1);
//**********************************************
// View data in CCS graph
//**********************************************
if( usStartSaveData == 1 )
{
saveIndex++;
if( (bufferFull == 0) && (samplePace <= saveIndex) )
{
Adc1[resultsIndex] = spll1.theta[0] * 100.0;
Adc2[resultsIndex] = fVan2* 100.0;
Adc3[resultsIndex] = park1.Qs * 100.0;
Adc4[resultsIndex] = FLTQs * 100.0; //fVdcref_gridFLT
/* Adc1[resultsIndex] = fVan2 * 100.0;
Adc2[resultsIndex] = fVbn2 * 100.0;
Adc3[resultsIndex] = cclarke1.Alpha * 100.0;
Adc4[resultsIndex] = clarke1.Beta * 100.0; //fVdcref_gridFLT*/
resultsIndex++;
saveIndex = 0;
}
if(RESULTS_BUFFER_SIZE <= resultsIndex)
{
resultsIndex = 0;
bufferFull = 1;
saveIndex = 0;
usStartSaveData = 0;
}
}
// GpioDataRegs.GPACLEAR.bit.GPIO8 = 1;
AdcaRegs.ADCINTFLGCLR.bit.ADCINT1 = 1; //clear INT1 flag
PieCtrlRegs.PIEACK.all = PIEACK_GROUP1;
}
//
// InitEPwm - Initialize EPWMx configuration
//
void InitEPwm()
{
fTdb = 250.0; // ns
fTdb2 = 250.0; // ns
fTdb3 = 250.0; // ns
EPwm1_DB = (Uint16)(fTdb * 0.1);
EPwm2_DB = (Uint16)(fTdb2 * 0.1);
EPwm3_DB = (Uint16)(fTdb3 * 0.1);
fDutyCycle = 0.3;
usPhase = (Uint16)(0.666666 * 0.5 * (float32)DC_DC_CONTROL_TBPRD);
usPwm2Phase = usPhase; // Phase B Main
usPwm3Phase = usPhase; // Phase C Main
EPwm1Regs.TBPRD = (Uint16)(0.5 * (float32)DC_DC_CONTROL_TBPRD); // Set timer period
EPwm1Regs.TBPHS.bit.TBPHS = 0x0000; // Phase is 0
EPwm1Regs.TBCTR = 0x0000; // Clear counter
EPwm1Regs.TBCTL.bit.CTRMODE = TB_COUNT_UPDOWN; // Count up-down
EPwm1Regs.TBCTL.bit.PHSEN = TB_DISABLE; // Disable phase loading
EPwm1Regs.TBCTL.bit.PRDLD = TB_SHADOW;
EPwm1Regs.TBCTL.bit.SYNCOSEL = TB_CTR_ZERO; // Sync Output Select: CTR = zero
// EPwm1Regs.rsvd2[0] = 0x0002; // EPWMxSYNCOUT Source Enable Register
EPwm1Regs.TBCTL.bit.HSPCLKDIV = TB_DIV1; // Clock ratio to SYSCLKOUT
EPwm1Regs.TBCTL.bit.CLKDIV = TB_DIV1;
EPwm1Regs.CMPCTL.bit.SHDWAMODE = CC_SHADOW; // Load registers every ZERO
EPwm1Regs.CMPCTL.bit.SHDWBMODE = CC_SHADOW;
EPwm1Regs.CMPCTL.bit.LOADAMODE = CC_CTR_ZERO;
EPwm1Regs.CMPCTL.bit.LOADBMODE = CC_CTR_ZERO;
// EPwm1Regs.CMPA.bit.CMPA = (Uint16)(fDutyCycle * (float32)CONTROL_TBPRD);
EPwm1Regs.AQCTLA.bit.CAU = AQ_CLEAR; // Set PWM1A on Zero
EPwm1Regs.AQCTLA.bit.CAD = AQ_SET;
EPwm1Regs.AQCTLB.bit.CAU = AQ_SET; // Set PWM1A on Zero
EPwm1Regs.AQCTLB.bit.CAD = AQ_CLEAR;
EPwm1Regs.AQSFRC.bit.RLDCSF = 3; // Load immediately
EPwm1Regs.DBCTL.bit.OUT_MODE = DB_FULL_ENABLE;
EPwm1Regs.DBCTL.bit.POLSEL = DB_ACTV_HIC;
EPwm1Regs.DBCTL.bit.IN_MODE = DBA_ALL;
EPwm1Regs.DBRED.bit.DBRED = EPwm1_DB;
EPwm1Regs.DBFED.bit.DBFED = EPwm1_DB;
EPwm2Regs.TBPRD = (Uint16)(0.5 * (float32)DC_DC_CONTROL_TBPRD); // Set timer period
EPwm2Regs.TBPHS.bit.TBPHS = usPwm2Phase; // Phase is 0
EPwm2Regs.TBCTR = 0x0000; // Clear counter
EPwm2Regs.TBCTL.bit.CTRMODE = TB_COUNT_UPDOWN; // Count up-down
EPwm2Regs.TBCTL.bit.PHSEN = TB_ENABLE; // Disable phase loading
EPwm2Regs.TBCTL.bit.PHSDIR = TB_DOWN; // Count down after the synchronization event
EPwm2Regs.TBCTL.bit.PRDLD = TB_SHADOW;
EPwm2Regs.TBCTL.bit.SYNCOSEL = TB_SYNC_IN;
// EPwm2Regs.rsvd2[0] = 0x0002; // EPWMxSYNCOUT Source Enable Register
EPwm2Regs.TBCTL.bit.HSPCLKDIV = TB_DIV1; // Clock ratio to SYSCLKOUT
EPwm2Regs.TBCTL.bit.CLKDIV = TB_DIV1;
EPwm2Regs.CMPCTL.bit.SHDWAMODE = CC_SHADOW; // Load registers every ZERO
EPwm2Regs.CMPCTL.bit.SHDWBMODE = CC_SHADOW;
EPwm2Regs.CMPCTL.bit.LOADAMODE = CC_CTR_ZERO;
EPwm2Regs.CMPCTL.bit.LOADBMODE = CC_CTR_ZERO;
// EPwm2Regs.CMPA.bit.CMPA = (Uint16)(fDutyCycle * (float32)CONTROL_TBPRD);
EPwm2Regs.AQCTLA.bit.CAU = AQ_CLEAR; // Set PWM1A on Zero
EPwm2Regs.AQCTLA.bit.CAD = AQ_SET;
EPwm2Regs.AQCTLB.bit.CAU = AQ_SET; // Set PWM1A on Zero
EPwm2Regs.AQCTLB.bit.CAD = AQ_CLEAR;
EPwm2Regs.AQSFRC.bit.RLDCSF = 3; // Load immediately
EPwm2Regs.DBCTL.bit.OUT_MODE = DB_FULL_ENABLE;
EPwm2Regs.DBCTL.bit.POLSEL = DB_ACTV_HIC;
EPwm2Regs.DBCTL.bit.IN_MODE = DBA_ALL;
EPwm2Regs.DBRED.bit.DBRED = EPwm2_DB;
EPwm2Regs.DBFED.bit.DBFED = EPwm2_DB;
EPwm3Regs.TBPRD = (Uint16)(0.5 * (float32)DC_DC_CONTROL_TBPRD); // Set timer period
EPwm3Regs.TBPHS.bit.TBPHS = usPwm3Phase; // Phase is 0
EPwm3Regs.TBCTR = 0x0000; // Clear counter
EPwm3Regs.TBCTL.bit.CTRMODE = TB_COUNT_UPDOWN; // Count up-down
EPwm3Regs.TBCTL.bit.PHSEN = TB_ENABLE; // Disable phase loading
EPwm3Regs.TBCTL.bit.PHSDIR = TB_UP; // Count down/up (0/1) after the synchronization event
EPwm3Regs.TBCTL.bit.PRDLD = TB_SHADOW;
EPwm3Regs.TBCTL.bit.SYNCOSEL = TB_SYNC_IN;
// EPwm3Regs.rsvd2[0] = 0x0002; // EPWMxSYNCOUT Source Enable Register
EPwm3Regs.TBCTL.bit.HSPCLKDIV = TB_DIV1; // Clock ratio to SYSCLKOUT
EPwm3Regs.TBCTL.bit.CLKDIV = TB_DIV1;
EPwm3Regs.CMPCTL.bit.SHDWAMODE = CC_SHADOW; // Load registers every ZERO
EPwm3Regs.CMPCTL.bit.SHDWBMODE = CC_SHADOW;
EPwm3Regs.CMPCTL.bit.LOADAMODE = CC_CTR_ZERO;
EPwm3Regs.CMPCTL.bit.LOADBMODE = CC_CTR_ZERO;
// EPwm3Regs.CMPA.bit.CMPA = (Uint16)(fDutyCycle * (float32)CONTROL_TBPRD);
EPwm3Regs.AQCTLA.bit.CAU = AQ_CLEAR; // Set PWM1A on Zero
EPwm3Regs.AQCTLA.bit.CAD = AQ_SET;
EPwm3Regs.AQCTLB.bit.CAU = AQ_SET; // Set PWM1A on Zero
EPwm3Regs.AQCTLB.bit.CAD = AQ_CLEAR;
EPwm3Regs.AQSFRC.bit.RLDCSF = 3; // Load immediately
EPwm3Regs.DBCTL.bit.OUT_MODE = DB_FULL_ENABLE;
EPwm3Regs.DBCTL.bit.POLSEL = DB_ACTV_HIC;
EPwm3Regs.DBCTL.bit.IN_MODE = DBA_ALL;
EPwm3Regs.DBRED.bit.DBRED = EPwm3_DB;
EPwm3Regs.DBFED.bit.DBFED = EPwm3_DB;
// PWM 4 used as ADC ISR
EPwm4Regs.TBPRD = INV_PWM_TBPRD_ADC; // Set timer period
EPwm4Regs.TBPHS.bit.TBPHS = 0x0000; // Phase is 0
EPwm4Regs.TBCTR = 0x0000; // Clear counter
EPwm4Regs.TBCTL.bit.CTRMODE = TB_COUNT_UPDOWN; // Count up-down
EPwm4Regs.TBCTL.bit.PHSEN = TB_DISABLE; // Disable phase loading
EPwm4Regs.TBCTL.bit.SYNCOSEL = 1; // Sync Output Select: CTR = zero
EPwm4Regs.rsvd2[0] = 0x0002; // EPWMxSYNCOUT Source Enable Register
EPwm4Regs.TBCTL.bit.HSPCLKDIV = TB_DIV1; // Clock ratio to SYSCLKOUT
EPwm4Regs.TBCTL.bit.CLKDIV = TB_DIV1;
// EPwm11Regs.CMPA.bit.CMPA = (Uint16)(fDutyCycle * (float32)INV_PWM_HALF_TBPRD);
EPwm4Regs.CMPCTL.bit.SHDWAMODE = CC_SHADOW; // Load registers every ZERO
EPwm4Regs.CMPCTL.bit.SHDWBMODE = CC_SHADOW;
EPwm4Regs.CMPCTL.bit.LOADAMODE = CC_CTR_ZERO_PRD;
EPwm4Regs.CMPCTL.bit.LOADBMODE = CC_CTR_ZERO_PRD;
EPwm4Regs.AQCTLA.bit.CAU = AQ_CLEAR; // Set PWM1A on Zero
EPwm4Regs.AQCTLA.bit.CAD = AQ_SET;
EPwm4Regs.AQCTLB.bit.CAU = AQ_SET; // Set PWM1A on Zero
EPwm4Regs.AQCTLB.bit.CAD = AQ_CLEAR;
EPwm4Regs.AQSFRC.bit.RLDCSF = 3; // Load immediately
EPwm4Regs.DBCTL.bit.OUT_MODE = DB_FULL_ENABLE;
EPwm4Regs.DBCTL.bit.POLSEL = DB_ACTV_HIC;
EPwm4Regs.DBCTL.bit.IN_MODE = DBA_ALL;
EPwm4Regs.DBRED.bit.DBRED = EPwm1_DB;
EPwm4Regs.DBFED.bit.DBFED = EPwm1_DB;
// Interrupt setting
// EPwm1Regs.ETSEL.bit.INTSEL = ET_CTR_ZERO; // Select INT on Zero event
// EPwm1Regs.ETPS.bit.INTPRD = ET_2ND; // Generate INT on 2nd event
// EPwm1Regs.ETSEL.bit.INTEN = 1; // Enable INT
// ADC SOC
EALLOW;
EPwm4Regs.ETSEL.bit.SOCASEL = 1; // Select SOC on Zero
EPwm4Regs.ETSEL.bit.SOCAEN = 1; //enable SOCA
EPwm4Regs.ETPS.bit.SOCAPRD = ET_1ST;// ET_1ST; // Generate pulse on ___ event
EDIS;
// EPwm1Regs.TBPRD = CONTROL_TBPRD; // Set timer period
// EPwm1Regs.TBPHS.bit.TBPHS = 0x0000; // Phase is 0
// EPwm1Regs.TBCTR = 0x0000; // Clear counter
// EPwm1Regs.TBCTL.bit.CTRMODE = TB_COUNT_UPDOWN; // Count up-down
// EPwm1Regs.TBCTL.bit.PHSEN = TB_DISABLE; // Disable phase loading
// EPwm1Regs.TBCTL.bit.SYNCOSEL = 1; // Sync Output Select: CTR = zero
// EPwm1Regs.rsvd2[0] = 0x0002; // EPWMxSYNCOUT Source Enable Register
// EPwm1Regs.TBCTL.bit.HSPCLKDIV = TB_DIV1; // Clock ratio to SYSCLKOUT
// EPwm1Regs.TBCTL.bit.CLKDIV = TB_DIV1;
// EPwm1Regs.CMPCTL.bit.SHDWAMODE = CC_SHADOW; // Load registers every ZERO
// EPwm1Regs.CMPCTL.bit.SHDWBMODE = CC_SHADOW;
// EPwm1Regs.CMPCTL.bit.LOADAMODE = CC_CTR_ZERO;
// EPwm1Regs.CMPCTL.bit.LOADBMODE = CC_CTR_ZERO;
// // EPwm1Regs.CMPA.bit.CMPA = (Uint16)(fDutyCycle * (float32)PWM_PRD_UD);
// EPwm1Regs.AQCTLA.bit.CAU = AQ_CLEAR; // Set PWM1A on Zero
// EPwm1Regs.AQCTLA.bit.CAD = AQ_SET;
// EPwm1Regs.AQCTLB.bit.CAU = AQ_SET; // Set PWM1A on Zero
// EPwm1Regs.AQCTLB.bit.CAD = AQ_CLEAR;
// EPwm1Regs.AQSFRC.bit.RLDCSF = 3; // Load immediately
// EPwm1Regs.DBCTL.bit.OUT_MODE = DB_FULL_ENABLE;
// EPwm1Regs.DBCTL.bit.POLSEL = DB_ACTV_HIC;
// EPwm1Regs.DBCTL.bit.IN_MODE = DBA_ALL;
// EPwm1Regs.DBRED.bit.DBRED = EPwm1_DB;
// EPwm1Regs.DBFED.bit.DBFED = EPwm1_DB;
// PWM modules for 3-phase inverter
// EPWM 7,8, 9
EPwm7Regs.TBPRD = INV_PWM_TBPRD; // Set timer period
EPwm7Regs.TBPHS.bit.TBPHS = 0x0000; // Phase is 0
EPwm7Regs.TBCTR = 0x0000; // Clear counter
EPwm7Regs.TBCTL.bit.CTRMODE = TB_COUNT_UPDOWN; // Count up-down
EPwm7Regs.TBCTL.bit.PHSEN = TB_DISABLE; // Disable phase loading
EPwm7Regs.TBCTL.bit.SYNCOSEL = 1; // Sync Output Select: CTR = zero
EPwm7Regs.rsvd2[0] = 0x0002; // EPWMxSYNCOUT Source Enable Register
EPwm7Regs.TBCTL.bit.HSPCLKDIV = TB_DIV1; // Clock ratio to SYSCLKOUT
EPwm7Regs.TBCTL.bit.CLKDIV = TB_DIV1;
// EPwm11Regs.CMPA.bit.CMPA = (Uint16)(fDutyCycle * (float32)INV_PWM_HALF_TBPRD);
EPwm7Regs.CMPCTL.bit.SHDWAMODE = CC_SHADOW; // Load registers every ZERO
EPwm7Regs.CMPCTL.bit.SHDWBMODE = CC_SHADOW;
EPwm7Regs.CMPCTL.bit.LOADAMODE = CC_CTR_ZERO_PRD;
EPwm7Regs.CMPCTL.bit.LOADBMODE = CC_CTR_ZERO_PRD;
EPwm7Regs.AQCTLA.bit.CAU = AQ_CLEAR; // Set PWM1A on Zero
EPwm7Regs.AQCTLA.bit.CAD = AQ_SET;
EPwm7Regs.AQCTLB.bit.CAU = AQ_SET; // Set PWM1A on Zero
EPwm7Regs.AQCTLB.bit.CAD = AQ_CLEAR;
EPwm7Regs.AQSFRC.bit.RLDCSF = 3; // Load immediately
EPwm7Regs.DBCTL.bit.OUT_MODE = DB_FULL_ENABLE;
EPwm7Regs.DBCTL.bit.POLSEL = DB_ACTV_HIC;
EPwm7Regs.DBCTL.bit.IN_MODE = DBA_ALL;
EPwm7Regs.DBRED.bit.DBRED = EPwm1_DB;
EPwm7Regs.DBFED.bit.DBFED = EPwm1_DB;
EPwm8Regs.TBPRD = INV_PWM_TBPRD; // Set timer period
EPwm8Regs.TBPHS.bit.TBPHS = 0x0000; // Phase is 0
EPwm8Regs.TBCTR = 0x0000; // Clear counter
EPwm8Regs.TBCTL.bit.CTRMODE = TB_COUNT_UPDOWN; // Count up-down
EPwm8Regs.TBCTL.bit.PHSEN = TB_DISABLE; // Disable phase loading
EPwm8Regs.TBCTL.bit.SYNCOSEL = 1; // Sync Output Select: CTR = zero
EPwm8Regs.rsvd2[0] = 0x0002; // EPWMxSYNCOUT Source Enable Register
EPwm8Regs.TBCTL.bit.HSPCLKDIV = TB_DIV1; // Clock ratio to SYSCLKOUT
EPwm8Regs.TBCTL.bit.CLKDIV = TB_DIV1;
// EPwm12Regs.CMPA.bit.CMPA = (Uint16)(fDutyCycle * (float32)INV_PWM_HALF_TBPRD);
EPwm8Regs.CMPCTL.bit.SHDWAMODE = CC_SHADOW; // Load registers every ZERO
EPwm8Regs.CMPCTL.bit.SHDWBMODE = CC_SHADOW;
EPwm8Regs.CMPCTL.bit.LOADAMODE = CC_CTR_ZERO_PRD;
EPwm8Regs.CMPCTL.bit.LOADBMODE = CC_CTR_ZERO_PRD;
EPwm8Regs.AQCTLA.bit.CAU = AQ_CLEAR; // Set PWM1A on Zero
EPwm8Regs.AQCTLA.bit.CAD = AQ_SET;
EPwm8Regs.AQCTLB.bit.CAU = AQ_SET; // Set PWM1A on Zero
EPwm8Regs.AQCTLB.bit.CAD = AQ_CLEAR;
EPwm8Regs.AQSFRC.bit.RLDCSF = 3; // Load immediately
EPwm8Regs.DBCTL.bit.OUT_MODE = DB_FULL_ENABLE;
EPwm8Regs.DBCTL.bit.POLSEL = DB_ACTV_HIC;
EPwm8Regs.DBCTL.bit.IN_MODE = DBA_ALL;
EPwm8Regs.DBRED.bit.DBRED = EPwm1_DB;
EPwm8Regs.DBFED.bit.DBFED = EPwm1_DB;
EPwm9Regs.TBPRD = INV_PWM_TBPRD; // Set timer period
EPwm9Regs.TBPHS.bit.TBPHS = 0x0000; // Phase is 0
EPwm9Regs.TBCTR = 0x0000; // Clear counter
EPwm9Regs.TBCTL.bit.CTRMODE = TB_COUNT_UPDOWN; // Count up-down
EPwm9Regs.TBCTL.bit.PHSEN = TB_DISABLE; // Disable phase loading
EPwm9Regs.TBCTL.bit.SYNCOSEL = 1; // Sync Output Select: CTR = zero
EPwm9Regs.rsvd2[0] = 0x0002; // EPWMxSYNCOUT Source Enable Register
EPwm9Regs.TBCTL.bit.HSPCLKDIV = TB_DIV1; // Clock ratio to SYSCLKOUT
EPwm9Regs.TBCTL.bit.CLKDIV = TB_DIV1;
// EPwm9Regs.CMPA.bit.CMPA = (Uint16)(fDutyCycle * (float32)INV_PWM_HALF_TBPRD);
EPwm9Regs.CMPCTL.bit.SHDWAMODE = CC_SHADOW; // Load registers every ZERO
EPwm9Regs.CMPCTL.bit.SHDWBMODE = CC_SHADOW;
EPwm9Regs.CMPCTL.bit.LOADAMODE = CC_CTR_ZERO_PRD;
EPwm9Regs.CMPCTL.bit.LOADBMODE = CC_CTR_ZERO_PRD;
EPwm9Regs.AQCTLA.bit.CAU = AQ_CLEAR; // Set PWM1A on Zero
EPwm9Regs.AQCTLA.bit.CAD = AQ_SET;
EPwm9Regs.AQCTLB.bit.CAU = AQ_SET; // Set PWM1A on Zero
EPwm9Regs.AQCTLB.bit.CAD = AQ_CLEAR;
EPwm9Regs.AQSFRC.bit.RLDCSF = 3; // Load immediately
EPwm9Regs.DBCTL.bit.OUT_MODE = DB_FULL_ENABLE;
EPwm9Regs.DBCTL.bit.POLSEL = DB_ACTV_HIC;
EPwm9Regs.DBCTL.bit.IN_MODE = DBA_ALL;
EPwm9Regs.DBRED.bit.DBRED = EPwm1_DB;
EPwm9Regs.DBFED.bit.DBFED = EPwm1_DB;
}
//
// ConfigureADC - Write ADC configurations and power up the ADC for both
// ADC A and ADC B
//
void ConfigureADC(void)
{
Uint16 acqps;
EALLOW;
//write configurations
AdcaRegs.ADCCTL2.bit.PRESCALE = 2; //set ADCCLK divider to /2.0
AdcSetMode(ADC_ADCA, ADC_RESOLUTION_12BIT, ADC_SIGNALMODE_SINGLE);
//Set pulse positions to late
AdcaRegs.ADCCTL1.bit.INTPULSEPOS = 1;
//power up the ADC
AdcaRegs.ADCCTL1.bit.ADCPWDNZ = 1;
//delay for 1ms to allow ADC time to power up
DELAY_US(1000);
EDIS;
// Determine minimum acquisition window (in SYSCLKS) based on resolution
if(ADC_RESOLUTION_12BIT == AdcaRegs.ADCCTL2.bit.RESOLUTION)
{
acqps = 14; //75ns
}
else //resolution is 16-bit
{
acqps = 63; //320ns
}
//Select the channels to convert and end of conversion flag
EALLOW;
AdcaRegs.ADCSOC0CTL.bit.CHSEL = 0; //SOC0 will convert pin A0
AdcaRegs.ADCSOC0CTL.bit.ACQPS = acqps; //sample window is 100 SYSCLK cycles
AdcaRegs.ADCSOC0CTL.bit.TRIGSEL = ADCTRIG; //ADCTRIG9 - ePWM3, ADCSOCA, ADCTRIG5 - ePWM1, ADCSOCA
AdcaRegs.ADCSOC1CTL.bit.CHSEL = 1;
AdcaRegs.ADCSOC1CTL.bit.ACQPS = acqps;
AdcaRegs.ADCSOC1CTL.bit.TRIGSEL = ADCTRIG;
AdcaRegs.ADCSOC2CTL.bit.CHSEL = 2;
AdcaRegs.ADCSOC2CTL.bit.ACQPS = acqps;
AdcaRegs.ADCSOC2CTL.bit.TRIGSEL = ADCTRIG;
AdcaRegs.ADCSOC3CTL.bit.CHSEL = 3;
AdcaRegs.ADCSOC3CTL.bit.ACQPS = acqps;
AdcaRegs.ADCSOC3CTL.bit.TRIGSEL = ADCTRIG;
AdcaRegs.ADCSOC4CTL.bit.CHSEL = 4;
AdcaRegs.ADCSOC4CTL.bit.ACQPS = acqps;
AdcaRegs.ADCSOC4CTL.bit.TRIGSEL = ADCTRIG;
AdcaRegs.ADCSOC5CTL.bit.CHSEL = 5;
AdcaRegs.ADCSOC5CTL.bit.ACQPS = acqps;
AdcaRegs.ADCSOC5CTL.bit.TRIGSEL = ADCTRIG;
AdcaRegs.ADCSOC6CTL.bit.CHSEL = 14;
AdcaRegs.ADCSOC6CTL.bit.ACQPS = acqps;
AdcaRegs.ADCSOC6CTL.bit.TRIGSEL = ADCTRIG;
AdcaRegs.ADCSOC7CTL.bit.CHSEL = 15;
AdcaRegs.ADCSOC7CTL.bit.ACQPS = acqps;
AdcaRegs.ADCSOC7CTL.bit.TRIGSEL = ADCTRIG;
AdcaRegs.ADCINTSEL1N2.bit.INT1SEL = 5; //end of SOCx will set INT1 flag
AdcaRegs.ADCINTSEL1N2.bit.INT1E = 1; //enable INT1 flag
AdcaRegs.ADCINTFLGCLR.bit.ADCINT1 = 1; //make sure INT1 flag is cleared
EDIS;
//For ADC-B
EALLOW;
//write configurations
AdcbRegs.ADCCTL2.bit.PRESCALE = 2; //set ADCCLK divider to /2.0
AdcSetMode(ADC_ADCB, ADC_RESOLUTION_12BIT, ADC_SIGNALMODE_SINGLE);
//Set pulse positions to late
AdcbRegs.ADCCTL1.bit.INTPULSEPOS = 1;
//power up the ADC
AdcbRegs.ADCCTL1.bit.ADCPWDNZ = 1;
//delay for 1ms to allow ADC time to power up
DELAY_US(1000);
EDIS;
// Determine minimum acquisition window (in SYSCLKS) based on resolution
if(ADC_RESOLUTION_12BIT == AdcbRegs.ADCCTL2.bit.RESOLUTION)
{
acqps = 14; //75ns
}
else //resolution is 16-bit
{
acqps = 63; //320ns
}
//Select the channels to convert and end of conversion flag
EALLOW;
AdcbRegs.ADCSOC0CTL.bit.CHSEL = 0; //SOC0 will convert pin B0
AdcbRegs.ADCSOC0CTL.bit.ACQPS = acqps; //sample window is 100 SYSCLK cycles
AdcbRegs.ADCSOC0CTL.bit.TRIGSEL = ADCTRIG; //ADCTRIG9 - ePWM3, ADCSOCA, ADCTRIG5 - ePWM1, ADCSOCA
AdcbRegs.ADCSOC1CTL.bit.CHSEL = 1;
AdcbRegs.ADCSOC1CTL.bit.ACQPS = acqps;
AdcbRegs.ADCSOC1CTL.bit.TRIGSEL = ADCTRIG;
AdcbRegs.ADCSOC2CTL.bit.CHSEL = 2;
AdcbRegs.ADCSOC2CTL.bit.ACQPS = acqps;
AdcbRegs.ADCSOC2CTL.bit.TRIGSEL = ADCTRIG;
AdcbRegs.ADCSOC3CTL.bit.CHSEL = 3;
AdcbRegs.ADCSOC3CTL.bit.ACQPS = acqps;
AdcbRegs.ADCSOC3CTL.bit.TRIGSEL = ADCTRIG;
AdcbRegs.ADCSOC4CTL.bit.CHSEL = 4;
AdcbRegs.ADCSOC4CTL.bit.ACQPS = acqps;
AdcbRegs.ADCSOC4CTL.bit.TRIGSEL = ADCTRIG;
AdcbRegs.ADCSOC5CTL.bit.CHSEL = 5;
AdcbRegs.ADCSOC5CTL.bit.ACQPS = acqps;
AdcbRegs.ADCSOC5CTL.bit.TRIGSEL = ADCTRIG;
AdcbRegs.ADCINTSEL1N2.bit.INT1SEL = 5; //end of SOCx will set INT1 flag
AdcbRegs.ADCINTSEL1N2.bit.INT1E = 1; //enable INT1 flag
AdcbRegs.ADCINTFLGCLR.bit.ADCINT1 = 1; //make sure INT1 flag is cleared
EDIS;
//For ADC-D
EALLOW;
//write configurations
AdcdRegs.ADCCTL2.bit.PRESCALE = 2; //set ADCCLK divider to /2.0
AdcSetMode(ADC_ADCD, ADC_RESOLUTION_12BIT, ADC_SIGNALMODE_SINGLE);
//Set pulse positions to late
AdcdRegs.ADCCTL1.bit.INTPULSEPOS = 1;
//power up the ADC
AdcdRegs.ADCCTL1.bit.ADCPWDNZ = 1;
//delay for 1ms to allow ADC time to power up
DELAY_US(1000);
EDIS;
// Determine minimum acquisition window (in SYSCLKS) based on resolution
if(ADC_RESOLUTION_12BIT == AdcdRegs.ADCCTL2.bit.RESOLUTION)
{
acqps = 14; //75ns
}
else //resolution is 16-bit
{
acqps = 63; //320ns
}
//Select the channels to convert and end of conversion flag
EALLOW;
AdcdRegs.ADCSOC0CTL.bit.CHSEL = 0; //SOC0 will convert pin B0
AdcdRegs.ADCSOC0CTL.bit.ACQPS = acqps; //sample window is 100 SYSCLK cycles
AdcdRegs.ADCSOC0CTL.bit.TRIGSEL = ADCTRIG; //ADCTRIG9 - ePWM3, ADCSOCA, ADCTRIG5 - ePWM1, ADCSOCA
AdcdRegs.ADCSOC1CTL.bit.CHSEL = 1;
AdcdRegs.ADCSOC1CTL.bit.ACQPS = acqps;
AdcdRegs.ADCSOC1CTL.bit.TRIGSEL = ADCTRIG;
AdcdRegs.ADCSOC2CTL.bit.CHSEL = 2;
AdcdRegs.ADCSOC2CTL.bit.ACQPS = acqps;
AdcdRegs.ADCSOC2CTL.bit.TRIGSEL = ADCTRIG;
AdcdRegs.ADCSOC3CTL.bit.CHSEL = 3;
AdcdRegs.ADCSOC3CTL.bit.ACQPS = acqps;
AdcdRegs.ADCSOC3CTL.bit.TRIGSEL = ADCTRIG;
AdcdRegs.ADCSOC4CTL.bit.CHSEL = 4;
AdcdRegs.ADCSOC4CTL.bit.ACQPS = acqps;
AdcdRegs.ADCSOC4CTL.bit.TRIGSEL = ADCTRIG;
AdcdRegs.ADCINTSEL1N2.bit.INT1SEL = 5; //end of SOCx will set INT1 flag
AdcdRegs.ADCINTSEL1N2.bit.INT1E = 1; //enable INT1 flag
AdcdRegs.ADCINTFLGCLR.bit.ADCINT1 = 1; //make sure INT1 flag is cleared
EDIS;
}
void Shutdown(void)
{
// software forced low on PWMA and PWMB
// EPwm1Regs.AQCSFRC.bit.CSFA = 1;
// EPwm1Regs.AQCSFRC.bit.CSFB = 1; // ***** THIS LINE HAS NO EFFECT ON PWMB *****
// PWM1B STAYS HIGH
EALLOW;
GpioCtrlRegs.GPAMUX1.bit.GPIO0 = 0;
GpioCtrlRegs.GPAMUX1.bit.GPIO1 = 0;
GpioCtrlRegs.GPAMUX1.bit.GPIO2 = 0;
GpioCtrlRegs.GPAMUX1.bit.GPIO3 = 0;
GpioCtrlRegs.GPAMUX1.bit.GPIO4 = 0;
GpioCtrlRegs.GPAMUX1.bit.GPIO5 = 0;
GpioCtrlRegs.GPAMUX1.bit.GPIO6 = 0;
GpioCtrlRegs.GPAMUX1.bit.GPIO7 = 0;
GpioCtrlRegs.GPAMUX1.bit.GPIO8 = 0;
GpioCtrlRegs.GPAMUX1.bit.GPIO9 = 0;
GpioCtrlRegs.GPAMUX1.bit.GPIO10 = 0;
GpioCtrlRegs.GPAMUX1.bit.GPIO11 = 0;
GpioCtrlRegs.GPADIR.bit.GPIO0 = 1; // output
GpioCtrlRegs.GPADIR.bit.GPIO1 = 1; // output
GpioCtrlRegs.GPADIR.bit.GPIO2 = 1; // output
GpioCtrlRegs.GPADIR.bit.GPIO3 = 1; // output
GpioCtrlRegs.GPADIR.bit.GPIO4 = 1; // output
GpioCtrlRegs.GPADIR.bit.GPIO5 = 1; // output
GpioCtrlRegs.GPADIR.bit.GPIO6 = 1; // output
GpioCtrlRegs.GPADIR.bit.GPIO7 = 1; // output
GpioCtrlRegs.GPADIR.bit.GPIO8 = 1; // output
GpioCtrlRegs.GPADIR.bit.GPIO9 = 1; // output
GpioCtrlRegs.GPADIR.bit.GPIO10 = 1; // output
GpioCtrlRegs.GPADIR.bit.GPIO11 = 1; // output
EDIS;
GpioDataRegs.GPACLEAR.bit.GPIO0 = 1;
GpioDataRegs.GPACLEAR.bit.GPIO1 = 1;
GpioDataRegs.GPACLEAR.bit.GPIO2 = 1;
GpioDataRegs.GPACLEAR.bit.GPIO3 = 1;
GpioDataRegs.GPACLEAR.bit.GPIO4 = 1;
GpioDataRegs.GPACLEAR.bit.GPIO5 = 1;
GpioDataRegs.GPACLEAR.bit.GPIO6 = 1;
GpioDataRegs.GPACLEAR.bit.GPIO7 = 1;
GpioDataRegs.GPACLEAR.bit.GPIO8 = 1;
GpioDataRegs.GPACLEAR.bit.GPIO9 = 1;
GpioDataRegs.GPACLEAR.bit.GPIO10 = 1;
GpioDataRegs.GPACLEAR.bit.GPIO11 = 1;
usRunState = FAULT;
usResumePWM = 0;
fDutyCycle = 0.0;
fDutyCycle2 = 0.0;
fDutyCycle3 = 0.0;
EPwm1_CMP = 0;
EPwm2_CMP = 0;
EPwm3_CMP = 0;
fVerr = 0.0;
fInt2 = 0.0;
fVoltCtrl = 0.0;
fIerrA = 0.0;
fIerrB = 0.0;
fIerrC = 0.0;
fIntA = 0.0;
fIntB = 0.0;
fIntC = 0.0;
fCurrCtrlA = 0.0;
fCurrCtrlB = 0.0;
fCurrCtrlC = 0.0;
}
//
// End of file
//
//Settings.h
/*
* values_functions_definition.h
*
* Created on: Dec 30, 2015
* Author: Jinia Roy
*/
#include "IQmathLib.h"
#include "F28x_Project.h"
#include "math.h"
#include "float.h"
#include "clarke.h"
#include "ipark.h"
#include "park.h"
#include "park_m.h"
#include "svgen.h"
#include "rmp_cntl.h"
#include "rampgen.h"
#include "volt_calc.h"
#include "dlog_4ch_f.h"
#include "svgen_dpwm_240.h"
#define PI (3.141592653589793238462643)
#define TWO_PI (6.283185307179586476925286)
#define PI_DIV6 (0.5235987756)
#define FOUR_PI_DIV3 (4.188790204)
#define TWO_PI_DIV3 (2.09439510239)
#define SQRT_THREE (1.7320508075)
#define SQRT_THREE_RECIP (0.57735027)
#define GRID_FREQ (60.0)
#define PWM_FREQUENCY (10000.0)
#define DC_DC_FREQUENCY (100000.0)
#define PWM_FREQUENCY_ADC (10000.0)
#define SYSTEM_FREQUENCY (100.0) // MHz
#define INV_PWM_TBPRD ( (SYSTEM_FREQUENCY * 1000000.0/2.0) / (PWM_FREQUENCY) )
#define INV_PWM_TBPRD_ADC ( (SYSTEM_FREQUENCY * 1000000.0/2.0) / (PWM_FREQUENCY_ADC) )
#define INV_PWM_HALF_TBPRD ((INV_PWM_TBPRD)/2.0)
#define DC_DC_CONTROL_TBPRD ((SYSTEM_FREQUENCY * 1000000.0/2.0) / (DC_DC_FREQUENCY) )
#define SAMPLING_PERIOD (1/(PWM_FREQUENCY_ADC)) //(1/(PWM_FREQUENCY))
#define SAMPLING_PERIOD_MORE 1/(100000)
#define CONTROL_PERIOD SAMPLING_PERIOD
#define MIN_DUTY (0.05)
#define MAX_DUTY (0.95)
#define NORMAL 0
#define OVER_CURRENT 1
#define OVER_VOLTAGE 2
#define FAULT 3
#define ACTIVE 1
#define ADCTRIG (11)
#define AdcFsVoltage 3.0
#define AdcBufLen 50
#define ABS(x) ( (x) > 0.0 ? (x) : (-(x)) )
#define MAX_THREE(A, B, C) ( (A) > (B) ? ( (A) > (C) ? (A) : (C) ) : ( (B) > (C) ? (B) : (C)) )
#define MIN_THREE(A, B, C) ( (A) < (B) ? ( (A) < (C) ? (A) : (C) ) : ( (B) < (C) ? (B) : (C)) )
#define UP_DOWN_LIMIT(x, U, D) \
x = ( ((x) > (D)) ? (x) : (D) ); \
x = ( ((x) < (U)) ? (x) : (U) ); \
// y += w_lpf * Ts * (x - y)
#define EMATH_OneOrderLpf(in, out, wT) \
out += (wT) * ( (in) - (out) );
float Iin_control(float);
float Vout_control(float);
float Vout_Controller_Predictor(float);
float Vout_control_type_three(float);
