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TMS320F280025: How to balance two interrupt functions?

Lu Hang
Prodigy 225 points
Part Number: TMS320F280025


Dear expert:

   I set up two interrupt functions,the ADCA interrput of 50us and CPUTimer1 interrupt of 100us,The application in CPUTimer1 interrupt cost about 5us.So when ADCA interrput happened a little bit later than CPUTimer1 interrupt becuause of ADC sampling.Even if  ADCA interrput has a higher priority than CPUTimer1 interrupt,ADCA interrput still need to wait the CPUTimer1 interrupt to finish it's application.The following is my test result.ADCA interrput's period is sometimes not steady because of waiting for the CPUTimer1 interrupt to finish:

If I make the ADCA interrput  to be able break the CPUTimer1 interrupt.The CPUTimer1 interrupt might wait for the application in ADCA interrput to be finished for a long time.How can I make CPUTimer1 interrupt happened just after the application is finished and exit the ADCA interrput.Then they will not interface each other.Initialize the CPUTimer1's conter with a special value?Could you give me some guiding ideas?

  • 0
    TI__Guru 62975 points

    Lu Hang,

    In general, the interrupt architecture for C28x works best when the ISR execution times are kept to an absolute minimum in such a way that real-time tasks are only blocked for an acceptable amount of time when simultaneous interrupts request servicing.

    Can you provide additional information on the ISRs tasks to help me understood what options might be helpful? More specifically for each ISR:

    • Are real-time deadlines involved?
    • Are there jitter requirements for execution?
    • Can any of the tasks be offloaded to the background loop?

    If the rate of interrupt generation between the ADCA and TIMER1 follows a constant, whole number ratio (like 2:1 for 100us:50us), the easiest solution might be to migrate the TIMER1 ISR tasks into the end of the ADCA ISR in such a way that they only run every 2nd ISR execution (for example, when ADCA_counter++ % 2 == 0) after the critical, real-time tasks are completed.

    Another option for a fixed timing relationship with separate ISRs might be to trigger the ADC SOC and periodic task using the same TIMER, EPWM, or coherent EPWMs. With a coherent timebase, you can ensure that the ADCA interrupt is always generated before the periodic interrupt.

    If any of the periodic tasks do not have real-time deadlines, they can be moved to the background loop where the tasks will run at a loose approximation of 100us while still being fully interruptible by the ADCA ISR. This can be accomplished through a background scheduler that monitors and services the TIMER entirely through periodic polling, or by using a hybrid scheme where the TIMER ISR handles some very fast, high priority tasks and then sets a global flag to let the background loop know when to execute the low priority tasks.

    -Tommy